TLV320AIC3204: Pops during powerup on HPL/HPR

Hi Joe,

Take a look at section 2.2.3.1 of this app note regarding pop-free operation and see if it helps your issue: https://www.ti.com/lit/ml/slaa557/slaa557.pdf

Brian

Thanks, Brian. 

Please note that the pop occurs on powerup (when LDOIN is applied), prior to programming, so I don't think it's an issue that can be solved by register programming.

Unless the chip can be powered only by IOVDD, and programmed, and then LDOIN gets turned on? That doesn't seem right either.

Testing is done with good quality ~60ohm headphones fwiw.

In that case I would recommend looking at this app note regarding power supply considerations: https://www.ti.com/lit/an/slaa492a/slaa492a.pdf

It also has recommendations on how to mitigate pop on power up.

Thanks.  I had already reviewed this document and followed its guidance, but it is still not working.

Figure 2 doesn't apply, as I don't have separate 1.8V supplies.  I am using the internal LDO (LDO_SELECT high).

I have two 3.3V sources available - a "dirty" one for IOVDD, and a clean one for LDOin.  Turning on LDOin some time after IOVDD is powered causes a pop.

If I connect IOVDD to LDOin, and use a diode as shown in Figure 4, I still get a loud pop.  What am I overlooking?  There must be something else going on.

Does the pop happen if you hold the RESET pin low the entire time? I'd like to know if it's due to the device coming out of reset or something else. At this point, it might be helpful to see your schematic.. or are you using the TI EVM?

It pops when power to LDOIN is applied, even if ^RESET is held down.  This happens whether LDOIN is connected to IOVDD or if it's applied after.

Schematic of the TLV section below.  D409 is PMEG3020EJ,115 as I mentioned.  3.3V and 3.3VA come from different regulators (3.3VA is cleaner for analog), and the intent was to apply it separately for shutdown power savings as well.

I'm sure it's something silly I'm overlooking, but I just can't find it.

OK, one thing I notice is that you are enabling the LDO, in that mode DVDD will generate it's own supply. Just want to make sure you are not also supplying a separate 1.8V at that point.

Otherwise, the pop is due to the charging of the caps on the HPL and HPR outputs. I would recommend removing the passives one by one there and see if it changes the pop (100ohm, 22nF, and 49.9k). Also, what kind of load are you connecting to observe the pop?

Correct, no 1.8V is being supplied from elsewhere.

I'll try removing the passives one by one, but they all serve a purpose. Ironically the 49.9k to prevent plug-in pops!

I'm using a high quality pair of headphones, but the design is primarily intended for line output.  (headphone is an option for versatility, might as well.)

OK, let me know how it goes. You could also sanity check your supplies by grabbing a scope plot of them ramping up and ensure they are stable at the time of the pop. Putting the HP output on the same scope capture might show how the supply ramp up and pop are related. Just some additional ideas for debugging.

Thanks!  I tried changing the passives but they just change the filtering characteristics of the pop.

Here's the power timing I see:

Blue and magenta are AVDD and DVDD.  Yellow is LDOIN.  IOVDD is applied many seconds before all of this happens.  Cyan is HPL showing the spike.  It always happens right when power is applied.  RESET is held low during this time.

I would have expected to see DVDD track LDOIN more closely, per Fig 5 in sla492a:

Not really sure why this is (or if it's important).

I guess I could add output resistance to slow all this down, but it seems like a hack.  Aren't I doing all the standard/correct things to prevent a pop at poweron?

Very puzzled by all this!

Hi Joe,

I am out of the office for business travel, but to give you a brief response, are you able to match the diagram where reset goes high and then AVDD goes high at the end instead of matching DVDD?

Brian