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Original question:

TPS793: LDO latches up (?) or otherwise conducts a ton of current

TLV320ADC3101: Could you disable AVDD if you're not using the chip (but DVDD and IOVDD stay on)?

Veselin Georgiev
Prodigy 40 points
Part Number: TLV320ADC3101

There's a related thread, where I posted about a problem with the LDO (TPS79330) I use to supply the AVDD for the TLV320ADC3101.

One relatively simple solution to that problem would be to disable the AVDD LDO (and the AVDD rail) entirely during the time the application sleeps to conserve battery. Of course, with AVDD = 0V, I don't expect any of the ADC functions to work; the rest of the device will be sleeping as well, so no I²C / I²S traffic would occur.

If the TLV320 can survive AVDD=0 for extended time, my plan of bringing it up upon device wake-up is to:

  • Enable the LDO (bringing AVDD to 3.0V) and wait a bit. IOVDD is 3.3V at all times, and DVDD is 1.8V at all times
  • Reset the TLV320 and then configure it for recording

When I want to put the device back to sleep, I plan to

  • Reset the TLV320 again, to enter the lowest-power state
  • Disable AVDD (it would slowly drain to 0V)
  • DVDD and IOVDD stay up even during sleep
  • This can go on for hours before the next wakeup

I don't see anything mentioned in the datasheet about this scenario. Would the behaviour of the TLV320 be undefined in that case? Could it be damaged by prolonged AVDD=0V while the other rails are powered? Do I need to take any extra steps besides the aforementioned?

Best regards,
Veselin

  • 0
    TI__Mastermind 23030 points

    Our suggestion is to apply reset. One out of reset the device is in low power mode and consumes very low current as shown in the enclosed snapshot.

    I do not suggest partial power up of chip

  • 0 in reply to Sanjay Dixit
    Prodigy 40 points

    Hi Sanjay,

    While the TLV320 can be configured to consume below 1 µA during sleep, the LDO that supplies AVDD itself consumes 180µA Iq, and we want to power that down as well, otherwise it eats precious battery. The solution (presented in the linked thread) provided for that, and supplied the TLV320 with an alternative, but noisier, AVDD during the power down state. However, this causes problems with the LDO we chose.

    One solution was to remove the extra circuitry that supplies the alternative and noisier power rail. This, however, means that AVDD becomes hard 0 volts when we disable the AVDD LDO.

    Hence the question here.

    I'm not trying to save 0.04µA, I'm trying to resolve a problem that appeared because of my attempts to save 180µA.

  • 0 in reply to Veselin Georgiev
    TI__Mastermind 46955 points

    Hi Veselin,

    Sanjay is investigating this for you. Apologies for the wait. You should hear from him by the end of the day.

    Best regards,

    Jeff

  • 0 in reply to Veselin Georgiev
    TI__Mastermind 23030 points

    This is an old device and so I do not have access to the internal connections of AVDD pin. Therefore I cannot comment with certainty on the consequences of powering down AVDD pin.

    As a possibility you could place a 1Mohm resistor from the noisy 3.3v supply to the AVDD Pin. Normally this would be a high impedance source and when LDO is on shall not have an effect on AVDD Pin. The 1Mohm 

    and Decoupling capacitor on AVDD would also block any noise from getting in this path.

    If in Power down we shut off the regulator and assert the reset of the ADC. The 1 M OHM would power up the AVDD pin. Its very low power requirement(0.04ua) would result in negligable drop and sufficant voltage to power the AVDD Line.

    Perhaps you could try this

  • 0 in reply to Sanjay Dixit
    Prodigy 40 points

    Hi Sanjay,

    I believe that may work, but I'm not sure whether 1M is not too high. Not because of the TLV320, but because of the LDO. From its datasheet, pg. 11, the functional block diagram of the LDO shows the internal feedback resistors and they are to the tune of 100kOhm to ground in total. I don't believe they are disconnected on LDO shutdown. So almost all of the current in the scenario you've drawn (LDO Off, TLV320 in 0.04µA sleep) would actually go through the LDO and that would bring the voltage down a lot.

  • +1 in reply to Veselin Georgiev
    TI__Mastermind 23030 points

    Hi Vesilin

    In that case perhaps we go down to about 27k and see what happens. Alternatively we keep the 1 M and put a Schottky(BAT44) in series with the LDO.