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Original question:

PCM1754-Q1: manual or external RESET

PCM1754: Internal Power On Reset function

Mochi
Genius 4005 points
Part Number: PCM1754

Hello,

Our customer applies Reset when input PCM data Fs is changed. Because in this sequence, sometime PCM1754 is made degradation of SNR issue, and it was solved by Reset.

Here is question, PCM1754 Power On Reset condition is Vcc>2.2Vmin as datasheet is described.

However in our experiment, it seems there is one more condition which is Vcom voltage also needs to less than 2.2V to assert internal POR.

Otherwise low SNR situation is not cleared. So actual device behavior shows somehow monitor Vcom and Vcc for POR.

As our countermeasure, we will apply long enough Vcc power down period to reach less than 2.2V Vcom.

Can you expect such internal connection path POR circuit to Vcom and our design approach is acceptable?

Regards,

Mochizuki

  • 0
    TI__Mastermind 24820 points

    Hello Mochizuki,

    Power on reset basically triggers the initialization sequence (which requires 1024 system clocks from the time VCC >  2.2 V)  so it only checks VCC . After the reset period, the internal register is initialized  and when ALL clks are also valid , the PCM provides proper analog output. So this reset  procedure is  not related to VCOM,  which is just the unbuffered common-mode voltage output.

    I can see how  an unsettled VCOM can effect SNR  but  POR doesn't monitor VCOM for its operation. During the reset period (1024 system clocks), the output is forced to VCC/2 and I suspect the VCOM is not yet at VCC/2 level  and thus degrades the SNR .If you monitor VCOM and VCC before and after initialization you should see some differences that is in line with above . 

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    Genius 4005 points

    Hi Arash,

    Thank you for your prompt reply and clarify Digital circuit initializing function.

     

    Here is capture of Vcc and Vcom voltage relation in this project.

    Actually when use 100uF for Vcom cap, SNR is untenable. In this case Vcom is keeping more than 2.3V.

    The other case, placed 10uF Vcom cap, the voltage reach to 0.8V during Vcc power down sequence and SNR is stable even dynamically change Fs.

     

    So far, we were facing PCM175x SNR unstable issue at several projects when change Fs during play mode.

    But we could not reach key mechanism of this mysterious phenomena, we thought SCK jitter and chance of POR timing bring this issue. But still not strong evidence we could get.

    In this project, we can see strong relation between Vcom potential during Vcc initializing process. It seems Analog circuit is required below curtain power down voltage at Vcom rail to recover the function at interface between DS modulator to Current switching circuit.

    Do you have any idea to expect root cause of this behavior?

     

    Regards,

    Mochizuki

    PCM1754 Vcom.pdf

  • 0 in reply to Mochi
    TI__Mastermind 24820 points

    Hello Mochizuki,

    This is in line with what I said above, the VCOM is not tracking VCC/2 due to using a bigger capacitor, You need to connect a 10uF cap not 100uF. Please refer to user's guide. Basically when POR is activated and chip is ready, you are still holding VCOM to a value that is not VCC/2. POR is doing its job and has nothing to do with value of VCOM. As long as you stay with recommended value of VCOM decupling cap, you should be okay.

    Regards,

    Arash