TLV320AIC3254: Beep Generator

Hi Miles,

I will look into your question and respond within the next 12-24 hours, thank you for your patience.

Kind regards,

Hi,

1. I plugged in PLL and clock coefficients into Audio CODEC/ADC PLL Calculator for 44.1k Fs and the values didn't satisfy PLL constraints.[ 1,1,7,560 - P,R,J,D] Perhaps these were the coefficients for 16k? Providing the correct I2S clocks in setup is essential to any output in DAC. Without tone generator is custom board having DAC output in LOR/LOL at 44.1?

2. Setting up beep generator in AIC3254 has pretty strict yet straightforward rules. I suggest running codec with 44.1 or 48Khz standard audio Fs and confirm DAC output. Then running example script in this app note for beep gen (https://www.ti.com/lit/an/slaa446/slaa446.pdf ) The example script is at 48kHz but its important to note the order in which the function was initialized no matter the frequency.

More information can be found in the reference guide :https://www.ti.com/lit/an/slaa408a/slaa408a.pdf?ts=1673469838737

Let me know if this works.

Kind regards,

Hello,

1. I put them into that sheet just now and I'm not seeing the issue, looks like it's generating 44.1k as expected:

2. I hadn't found the slaa446 document (I've been using the slaa408a), I will look it over.

You're correct, I must've inputted a different PLL_CLKIN earlier, let me know if you have any further questions

I've reconfigured my startup flow and beep generation values to match the example from slaa446, but still not getting a beep out.

Config and clock scripts are unchanged, but here's what I've got now for open and start:

AudioHAL_I2CReg openScript[] =
{
    {TI3254_PAGE_0, TI3254_DAC_SIG_P_BLK_CTRL_REG, 0x19},       /* Use PRB_P25: Beep generator */
    {TI3254_PAGE_0, TI3254_DAC_CHANNEL_SETUP_1_REG, 0xD6},      /* Left/Right channel DAC powered up and routed to left/right data. soft-stepping disabled */
     /* Set up AVdd as output controlled from LDOIN */
     {TI3254_PAGE_1, TI3254_PWR_CTRL_REG, 0x08},                             /* Disabled weak connection of AVdd with DVdd */
     {TI3254_PAGE_1, TI3254_LDO_CTRL_REG, 0x00},                             /* Analog blocks enabled, Power AVdd from LDO */
     {TI3254_PAGE_1, TI3254_REF_PWR_UP_CTRL_REG, 0x01},                      /* Set the REF charging time to 40ms */
    /* Setup DAC */
    {TI3254_PAGE_1, TI3254_OP_DRV_PWR_CTRL_REG, 0x08 | 0x04},           /* LOL and LOR power up */
    {TI3254_PAGE_1, TI3254_LOL_ROUTING_SEL_REG, 0x04},                       /* Right DAC Negative connected to LOL */
    {TI3254_PAGE_1, TI3254_LOR_ROUTING_SEL_REG, 0x04},                       /* Right DAC Positive connected to LOR */
    {TI3254_PAGE_1, TI3254_LOL_DRV_GAIN_CTRL_REG, 0x00},                /* LOL not muted, 0 dB gain */
    {TI3254_PAGE_1, TI3254_LOR_DRV_GAIN_CTRL_REG, 0x00},                /* LOR not muted, 0 dB gain */
    {TI3254_PAGE_0, TI3254_LEFT_DAC_VOL_CTRL_REG, 0x0C},                /* 6 dB */
    {TI3254_PAGE_0, TI3254_RIGHT_DAC_VOL_CTRL_REG, 0x0C},               /* 6 dB */
    {TI3254_PAGE_1, TI3254_COMMON_MODE_CONTROL_REG, 0x40},                   /* Full Chip Common Mode = 0.9v, LOL/LOR = 1.65V from LDOIN */
    {TI3254_PAGE_0, TI3254_DAC_CHANNEL_SETUP_2_REG, 0x00},              /* Left DAC not muted, Right DAC not muted,  */
    {TI3254_PAGE_1, 0x03, 0x02},
    {TI3254_PAGE_1, 0x04, 0x02},
};

AudioHAL_I2CReg startScript[] =
{
    {TI3254_PAGE_0, 0x49, 0x01},        /* Beep length [23:16] */
    {TI3254_PAGE_0, 0xAB, 0x77},        /* Beep length [15:8] */
    {TI3254_PAGE_0, 0x4B, 0x00},        /* Beep length [7:0] */
    {TI3254_PAGE_0, 0x4C, 0x23},        /* Beep sine [15:8] */
    {TI3254_PAGE_0, 0x4D, 0xFB},        /* Beep sine [7:0] */
    {TI3254_PAGE_0, 0x4E, 0x7A},        /* Beep cosine [15:8] */
    {TI3254_PAGE_0, 0x4F, 0xD7},        /* Beep cosine [7:0] */
    {TI3254_PAGE_0, 0x48, 0x03},        /* Right chan beep gain */
    {TI3254_PAGE_0, 0x47, 0x83},        /* Send beep and left chan beep gain */
};

Please wait for my response, will be before Monday 1/16

Hi, 

Please reference this thread: https://e2e.ti.com/support/audio-group/audio/f/audio-forum/773086/faq-tlv320aic3254-tlv320aic32xx-family-beep-generator-configuration

My comments:

• Noted in threads linked beep.txt, try enabling adaptive filtering for DAC after selecting PRB_P25 and before disabling weak AVDD
• Set the input power up time after enabling analog blocks; w 30 47 32

Miles Matton said:

{TI3254_PAGE_1, TI3254_LOL_ROUTING_SEL_REG, 0x04},                       /* Right DAC Negative connected to LOL */
    {TI3254_PAGE_1, TI3254_LOR_ROUTING_SEL_REG, 0x04},                       /* Right DAC Positive connected to LOR */

• By write 0x04 to both registers, you are routing Left DAC to LOL and writing over reserved bit in P1_R15, Writing 0x08 to both may solve problem here.
• You unmuted LOL/LOR driver but they haven't been powered up yet in P1_R9
• Following script in thread, you want to route LDAC/RDAC before power up

I haven't check beep coefficients yet, but let me know if changing configuration and playback setup resolves issue

Hey,

I can't view that BEEP.txt file in the other thread, it just gives me a page saying "You do not have permission to view this directory or page." so I'm really only going on what you said here.

I added / changed things to follow what you pointed out, but still not getting anything output. Here's the open script as it is now:

AudioHAL_I2CReg openScript[] =
{
     {TI3254_PAGE_0, TI3254_DAC_SIG_P_BLK_CTRL_REG, 0x19},       /* Use PRB_P25: Beep generator */
     {TI3254_PAGE_44, TI3254_DAC_ADP_FILTER_CTRL_REG, 0x04},                  /* Adaptive Filtering enabled for DAC */
     {TI3254_PAGE_0, TI3254_DAC_CHANNEL_SETUP_1_REG, 0xD6},      /* Left/Right channel DAC powered up and routed to left/right data. soft-stepping disabled */
     /* Set up AVdd as output controlled from LDOIN */
     {TI3254_PAGE_1, TI3254_PWR_CTRL_REG, 0x08},                             /* Disabled weak connection of AVdd with DVdd */
     {TI3254_PAGE_1, TI3254_LDO_CTRL_REG, 0x00},                             /* Analog blocks enabled, Power AVdd from LDO */
     {TI3254_PAGE_1, TI3254_ANALOG_IP_QCHRG_CTRL_REG, 0x32},    /* Set analog input power up time ??? */
     {TI3254_PAGE_1, TI3254_REF_PWR_UP_CTRL_REG, 0x01},                      /* Set the REF charging time to 40ms */
    /* Setup DAC */
    {TI3254_PAGE_1, TI3254_LOL_ROUTING_SEL_REG, 0x08},                       /* Right DAC Negative connected to LOL */
    {TI3254_PAGE_1, TI3254_LOR_ROUTING_SEL_REG, 0x08},                       /* Right DAC Positive connected to LOR */
    {TI3254_PAGE_1, TI3254_LOL_DRV_GAIN_CTRL_REG, 0x00},                /* LOL not muted, 0 dB gain */
    {TI3254_PAGE_1, TI3254_LOR_DRV_GAIN_CTRL_REG, 0x00},                /* LOR not muted, 0 dB gain */
    {TI3254_PAGE_1, TI3254_OP_DRV_PWR_CTRL_REG, 0x08 | 0x04},           /* LOL and LOR power up */
    {TI3254_PAGE_0, TI3254_LEFT_DAC_VOL_CTRL_REG, 0x0C},                /* 6 dB */
    {TI3254_PAGE_0, TI3254_RIGHT_DAC_VOL_CTRL_REG, 0x0C},               /* 6 dB */
    {TI3254_PAGE_1, TI3254_COMMON_MODE_CONTROL_REG, 0x40},                   /* Full Chip Common Mode = 0.9v, LOL/LOR = 1.65V from LDOIN */
    {TI3254_PAGE_0, TI3254_DAC_CHANNEL_SETUP_2_REG, 0x00},              /* Left DAC not muted, Right DAC not muted,  */
    {TI3254_PAGE_1, 0x03, 0x02},
    {TI3254_PAGE_1, 0x04, 0x02},
};

None of the other scripts had changes.

###############################################
# Software Reset
###############################################
#
# Select Page 0
w 30 00 00
#
# Initialize the device through software reset
w 30 01 01
#
###############################################



###############################################
# Clock and Interface Settings
# ---------------------------------------------
# The codec receives: MCLK = 11.2896 MHz,
# BLCK = 2.8224 MHz, WCLK = 44.1 kHz
###############################################
#
# Select Page 0
w 30 00 00
#
# PLL_clkin = MCLK, codec_clkin = PLL_CLK,
# PLL on, P=1, R=1, J=8, D=0000
w 30 04 03 91 08 00 00
#
# NDAC = 2, MDAC = 8, dividers powered on
w 30 0b 82 88
#
# DOSR = 128
w 30 0D 00 80
#
# NADC = 2, MADC = 8, dividers powered on
w 30 12 82 88
#
# AOSR = 128
w 30 14 80
#
###############################################



###############################################
# Configure Processing Blocks
###############################################
#
# Select Page 0
w 30 00 00
#
# PRB_P25 selected
w 30 3C 19
#
# Select Page 44, Enable Adaptive filtering for DAC
w 30 00 2c 04
#
###############################################



###############################################
# Configure Power Supplies
###############################################
#
# Select Page 1
w 30 00 01
#
# Disable weak AVDD in presence of external
# AVDD supply
w 30 01 08
#
# Enable Master Analog Power Control
w 30 02 00
#
# Set the input power-up time to 3.1ms (for ADC)
w 30 47 32
#
# Set the REF charging time to 40ms
w 30 7b 01
#
###############################################



###############################################
# Playback Setup
###############################################
#
# Select Page 1
w 30 00 01
#
# De-pop
w 30 14 25
#
# Route LDAC/RDAC to HPL/HPR
w 30 0c 08 08
#
# Route LDAC/RDAC to LOL/LOR
w 30 0e 08 08
#
# Power up HPL/HPR and LOL/LOR drivers
w 30 09 3C
#
# Unmute HPL/HPR driver, 0dB Gain
w 30 10 00 00
#
# Unmute LOL/LOR driver, 0dB Gain
w 30 12 00 00
#
# Select Page 0
w 30 00 00
#
# DAC => 0dB
w 30 41 00 00
#
# Power up LDAC/RDAC
w 30 3f d6
#
# Unmute LDAC/RDAC
w 30 40 00
#
###############################################



###############################################
# Beep Generator Settings
###############################################
#
# Select Page 0
w 30 00 00
#
# Gain = -6dB
w 30 47 0C 0C
#
# 1 second beep 44100ksps*1s
w 30 49 00 AC 44
#
# 2kHz at 44.1ksps
w 30 4C 23 FB
w 30 4E 7A D7
#
###############################################

This is code from thread, after following this format let me know if there are still any issues.

I also suggest powering up NADC/MADC dividers, device may not be receiving clocks.

I went through that example and mostly just reordered things, here's the latest version of the changed scripts:

AudioHAL_I2CReg clockRegs44p1k_m[] =
{
    {TI3254_PAGE_0, TI3254_CLK_MUX_REG, 0x03},                          /* Low Range, PLL Clock = MCLK, CODEC_CLKIN = PLL_Clock */
    {TI3254_PAGE_0, TI3254_CLK_PLL_P_R_REG, 0x80 | 0x10 | 0x01},        /* PLL is powered up, P=1, R=1 */
    {TI3254_PAGE_0, TI3254_CLK_PLL_J_REG, 0x07},                        /* J=7 */
    {TI3254_PAGE_0, TI3254_CLK_PLL_D_MSB_REG, 0x02},                    /* Set MSB of D value D=560 */
    {TI3254_PAGE_0, TI3254_CLK_PLL_D_LSB_REG, 0x30},                    /* Set LSB of D value */
    {TI3254_PAGE_0, TI3254_CLK_NDAC_REG, 0x80 | 0x05},                  /* NDAC divider powered up, NDAC = 5 */
    {TI3254_PAGE_0, TI3254_CLK_MDAC_REG, 0x80 | 0x03},                  /* MDAC divider powered up, MDAC = 3 */
    /* {TI3254_PAGE_0, TI3254_DAC_OSR_MSB_REG, 0x00},                      (default) DOSR = 128 */
    /* {TI3254_PAGE_0, TI3254_DAC_OSR_LSB_REG, 0x80},                      (default) DOSR = 128 */
    {TI3254_PAGE_0, TI3254_CLK_NADC_REG, 0x80 | 0x05},                  /* NADC divider powered up, NADC = 5 same as DAC */
    {TI3254_PAGE_0, TI3254_CLK_MADC_REG, 0x80 | 0x03},                  /* MADC divider powered up, MADC = 3 same as DAC */
    /* {TI3254_PAGE_0, TI3254_ADC_OSR_REG, 0x80},                          (default) AOSR = 128 ((Use with PRB_R1 to PRB_R6, ADC Filter Type A) */
    /* {TI3254_PAGE_0, TI3254_AUDIO_IF_3_REG, 0x00},                       (default) Primary BCLK and Primary WCLK buffers are powered up */
};

AudioHAL_I2CReg openScript[] =
{
    {TI3254_PAGE_0, TI3254_DAC_SIG_P_BLK_CTRL_REG, 0x19},       /* Use PRB_P25: Beep generator */
    {TI3254_PAGE_44, TI3254_DAC_ADP_FILTER_CTRL_REG, 0x04},                  /* Adaptive Filtering enabled for DAC */
    /* Set up AVdd as output controlled from LDOIN */
    {TI3254_PAGE_1, TI3254_PWR_CTRL_REG, 0x08},                             /* Disabled weak connection of AVdd with DVdd */
    {TI3254_PAGE_1, TI3254_LDO_CTRL_REG, 0x00},                             /* Analog blocks enabled, Power AVdd from LDO */
    {TI3254_PAGE_1, TI3254_ANALOG_IP_QCHRG_CTRL_REG, 0x32},    /* Set analog input power up time ??? */
    {TI3254_PAGE_1, TI3254_REF_PWR_UP_CTRL_REG, 0x01},                      /* Set the REF charging time to 40ms */
    {TI3254_PAGE_1, TI3254_HP_DRV_START_UP_CTRL_REG, 0x25}, /* De-pop for headphone ??? */
    /* Setup DAC */
    {TI3254_PAGE_1, TI3254_COMMON_MODE_CONTROL_REG, 0x40},                   /* Full Chip Common Mode = 0.9v, LOL/LOR = 1.65V from LDOIN */
    {TI3254_PAGE_1, TI3254_LOL_ROUTING_SEL_REG, 0x08},                       /* Right DAC Negative connected to LOL */
    {TI3254_PAGE_1, TI3254_LOR_ROUTING_SEL_REG, 0x08},                       /* Right DAC Positive connected to LOR */
    {TI3254_PAGE_1, TI3254_OP_DRV_PWR_CTRL_REG, 0x08 | 0x04},           /* LOL and LOR power up */
    {TI3254_PAGE_1, TI3254_LOL_DRV_GAIN_CTRL_REG, 0x00},                /* LOL not muted, 0 dB gain */
    {TI3254_PAGE_1, TI3254_LOR_DRV_GAIN_CTRL_REG, 0x00},                /* LOR not muted, 0 dB gain */
    {TI3254_PAGE_0, TI3254_LEFT_DAC_VOL_CTRL_REG, 0x0C},                /* 6 dB */
    {TI3254_PAGE_0, TI3254_RIGHT_DAC_VOL_CTRL_REG, 0x0C},               /* 6 dB */
    {TI3254_PAGE_0, TI3254_DAC_CHANNEL_SETUP_1_REG, 0xD6},      /* Left/Right channel DAC powered up and routed to left/right data. soft-stepping disabled */
    {TI3254_PAGE_0, TI3254_DAC_CHANNEL_SETUP_2_REG, 0x00},              /* Left DAC not muted, Right DAC not muted,  */
    {TI3254_PAGE_1, 0x03, 0x02},
    {TI3254_PAGE_1, 0x04, 0x02},
};

AudioHAL_I2CReg startScript[] =
{
    {TI3254_PAGE_0, 0x47, 0x03},        /* Left chan beep gain */
    {TI3254_PAGE_0, 0x48, 0x03},        /* Right chan beep gain */
    {TI3254_PAGE_0, 0x49, 0x00},        /* Beep length [23:16] */
    {TI3254_PAGE_0, 0xAB, 0xAC},        /* Beep length [15:8] */
    {TI3254_PAGE_0, 0x4B, 0x44},        /* Beep length [7:0] */
    {TI3254_PAGE_0, 0x4C, 0x23},        /* Beep sine [15:8] */
    {TI3254_PAGE_0, 0x4D, 0xFB},        /* Beep sine [7:0] */
    {TI3254_PAGE_0, 0x4E, 0x7A},        /* Beep cosine [15:8] */
    {TI3254_PAGE_0, 0x4F, 0xD7},        /* Beep cosine [7:0] */
    {TI3254_PAGE_0, 0x47, 0x83},        /* Send beep and left chan beep gain */
};

Still no luck though.

Hi,

I setup EVM and successfully played 1kHz tone through LOL/LOR, the issue is that the beep generator was not enabled in 0x47, so if you write 0x83 it should solve problem.

{TI3254_PAGE_0, 0x47, 0x83},        /* Left chan beep gain */

But I am setting that, it's the very last one in that start script.

Hi Miles,

Are you able to playback any sound through LOL/LOR without trying to generate beep?

Also try: 

    {TI3254_PAGE_0, 0x47, 0x83},        /* Send beep and left chan beep gain *
    {TI3254_PAGE_0, 0x48, 0x03},        /* Right chan beep gain */
    {TI3254_PAGE_0, 0x49, 0x00},        /* Beep length [23:16] */
    {TI3254_PAGE_0, 0xAB, 0xAC},        /* Beep length [15:8] */
    {TI3254_PAGE_0, 0x4B, 0x44},        /* Beep length [7:0] */
    {TI3254_PAGE_0, 0x4C, 0x23},        /* Beep sine [15:8] */
    {TI3254_PAGE_0, 0x4D, 0xFB},        /* Beep sine [7:0] */
    {TI3254_PAGE_0, 0x4E, 0x7A},        /* Beep cosine [15:8] */
    {TI3254_PAGE_0, 0x4F, 0xD7},        /* Beep cosine [7:0] */

No, I'm trying to use the beep as a source to test out the LOL/LOR sound, then work backwards from there (if the full audiopath doesn't work) one step at a time.

I tried it out, but didn't have any effect.

Ok, allow me some time to setup again closer to your setup

Hi,

I suspect this is an issue with your clock settings, my comments:

• Will your code not compile if full hex number is written to register or does it have to be in a certain format past 0x80?
• Could this script for clocks not suffice?

    {TI3254_PAGE_0, TI3254_CLK_MUX_REG, 0x03},     /* Low Range, PLL Clock = MCLK, CODEC_CLKIN = PLL_Clock */
   {TI3254_PAGE_0, TI3254_CLK_PLL_P_R_REG, 0x91},        /* PLL is powered up, P=1, R=1 */
    {TI3254_PAGE_0, TI3254_CLK_PLL_J_REG, 0x07},                        /* J=7 */
    {TI3254_PAGE_0, TI3254_CLK_PLL_D_MSB_REG, 0x02},                    /* Set MSB of D value D=560 */
    {TI3254_PAGE_0, TI3254_CLK_PLL_D_LSB_REG, 0x30},                    /* Set LSB of D value */
    {TI3254_PAGE_0, TI3254_CLK_NDAC_REG, 0x85},                  /* NDAC divider powered up, NDAC = 5 */
    {TI3254_PAGE_0, TI3254_CLK_MDAC_REG, 0x83},                  /* MDAC divider powered up, MDAC = 3 */
    /* {TI3254_PAGE_0, TI3254_DAC_OSR_MSB_REG, 0x00},                      (default) DOSR = 128 */
    /* {TI3254_PAGE_0, TI3254_DAC_OSR_LSB_REG, 0x80},                      (default) DOSR = 128 */
    {TI3254_PAGE_0, TI3254_CLK_NADC_REG, 0x85},                  /* NADC divider powered up, NADC = 5 same as DAC */
    {TI3254_PAGE_0, TI3254_CLK_MADC_REG, 0x83},                  /* MADC divider powered up, MADC = 3 same as DAC */
    {TI3254_PAGE_0, TI3254_ADC_OSR_REG, 0x80},                          (default) AOSR = 128 ((Use with PRB_R1 to PRB_R6, ADC Filter Type A)
    /* {TI3254_PAGE_0, TI3254_AUDIO_IF_3_REG, 0x00},                       (default) Primary BCLK and Primary WCLK buffers are powered down when codec if off */

Ultimately, the initialization script looks okay and schematic looks okay, I would confirm that DAC_Fs is correct, you route this to WCLK output. Also confirming that all clocks are correct as well

Thread is still open to comment

No, it doesn't require that format, that was just used to be more easily read & compare what bits are set to the documentation.

I tried it with that for the clock script, both with and without the TI3254_ADC_OSR_REG register being set because I think you'd meant to have it commented out, but I'm still not getting any sound out. I will set up the 'scope tomorrow to look at what's actually happening on those clock lines, anything you want me to look at that I didn't talk about in that previous post that was all about the clock?

Yep, it was the clocks again. Specifically, it was that TI3254_LDO_CTRL_REG register (again). D3 was cleared, same as for the fix for the other board, but D0 also was cleared, unlike the other one. Once D0 was set the PLL clock started working and now getting _something_ coming out LOL/LOR.