Hello,
TLV320AIC1106's data sheet defines only the Typ value of MCLK frequency, but how much frequency tolerance is allowed? I've never seen a clock that has no frequency error at all. The frequency error I've ever seen ranges from a few to about 100 ppm.
I guess the parameter "MCLK jitter" (Max 37%) includes not only what's generally called "clock jitter" itself but also the concept of frequency tolerance, but is my guess correct?
From the old E2E thread "How to interface MCU with PCM CODEC: TLV320AIC1106?" the TLV320AIC1106's MCLK jitter is a percentage of the MCLK period. Given the MCLK frequency is 2.048 MHz, the 37% is about 0.181 µs, which is too large for what's generally called "jitter" in the world — random jitter plus deterministic jitter. Therefore, I suspect that the 0.181 µs includes a clock frequency tolerance (1/(2,048 MHz)±0.181 µs → 2,048 MHz+59%/-27%).
Please confirm it and give me feedback.
Best regards,
Shinichi Yokota
