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TLV320ADC3101-Q1: acquisition waveform with MATLAB is not smooth

Kailyn Chen
Genius 9560 points
Part Number: TLV320ADC3101-Q1

Hello，

 Our customer used TLV320ADC3101-Q1 for his application, sampling rate is 32Kbps, Generating Master Clock from BCLK,

The captured data of ADC output which drew with MATLAB is not smooth as this:

Best regards

kailyn

But if configured 16Kbps sampling rate, the captured curve is smooth. 

  • 0
    TI__Mastermind 22890 points

    Hi Kailyn,

    I'm not fully understanding your question, are you wanting to troubleshoot the SDOUT of ADC3101-Q1 because the digitized sine wave is not a smooth curve?

    If so, can you provide what the system clocks input configurations are? You mentioned that you're providing MCLK to generate the lower jitter ASI clocks such as BCLK and FSYNC.

    Regards,

  • 0 in reply to Daveon Douglas
    Prodigy 20 points

    The digitized sine wave is not a smooth curve.

    The system clock generate master clock from BCLK，the configurations of registers as this picture：

    Use this equation to calculate parameters： fS= (PLLCLK_IN × K × R) / (NADC×MADC×AOSR × P)

    BCLK:32000*16*2=1024kHz,

    P=1，R=8，K=10.0，NADC=5，MADC=8，AOSR=64，

    fs=(1024 x 10 x8)/(5 x 8 x 64 x 1)=32k

    The ADC Processing Block is PRB_R8.

  • 0 in reply to jiameng cheng
    TI__Mastermind 22890 points

    Hi Jiameng,

    Just to clarify, customer see's smooth output at 16kHz sampling but a  distorted curve at 32kHz sampling?

    Comments:

    • Were the only changes made from 16Khz to 32kHz sampling were PLL coefficients?
    • If possible can you provide actual SDOUT waveform and THD+N response?
    • If you bypass miniDSP biquads, do you see a change in output?
    • What is the input signal level in Vrms?

    Best Regards,

  • 0 in reply to Daveon Douglas
    Prodigy 20 points

    Just to clarify, customer see's smooth output at 16kHz sampling but a  distorted curve at 32kHz sampling?--Yes.

    Comments:

    • Were the only changes made from 16Khz to 32kHz sampling were PLL coefficients?

                --no,the diffrent about 16Khz and 32kHz,as follow:

    16KhZ 32KhZ
    SAMPLE RATE(Hz) 16000 32000
    BCLK(Hz 512000 1024000
    P 1 1
    R 16 8
    K 10 10
    NADC 10 5
    MADC 4 8
    AOSR 128 64
    PRB_R PRB_R1 PRB_R8
    fs (512 x 10 x16)/(4 x 10 x 128 x 1)=16k (1024 x 10 x8)/(5 x 8 x 64 x 1)=32k
    • If possible can you provide actual SDOUT waveform and THD+N response?--Please refer to the attachment.
    • If you bypass miniDSP biquads, do you see a change in output?  --Do you mean to sellect a  processing blocks with 0 biquad? i have tried，but there has been no improvement.
    • What is the input signal level in Vrms? --input signal is 600mV vpp,the Vrms is 106mV.
    •  32000-adc.txt

  • 0 in reply to jiameng cheng
    TI__Mastermind 22890 points

    Hi Jiameng,

    Your register configurations and dividers seem correct. i have two suggestions:

    • You're providing a common integer BCLK and WCLK input so the PLL is not necessary. If you bypass the PLL and input highlighted below, do you see the same response in the output?

    • However you're processing your SDOUT (I assume MATLAB) may have some effect on the actual quality of audio in SDOUT. Can you use a different analyzer to monitor the performance here?

    Best Regards,