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HI
I'm Using TMS320C5535 board for Audio codec when i run the code it working fine but output has comes Beep sound and also collides so much noise voice arrived
These is my AIC3204 Inti.c file
/*****************************************************************************/
/* */
/* FILENAME */
/* aic3204_init.c */
/* */
/* DESCRIPTION */
/* Initialisation of the AIC3204 Codec. */
/* */
/* Sets up the codec for line inputs. */
/* Uses a sampling frequency of 48000 Hz. */
/* Note: "aic3204.h" needs to go after "usbstk5515.h" */
/* */
/* REVISION */
/* Revision: 1.00 */
/* Author : Richard Sikora */
/*---------------------------------------------------------------------------*/
/* */
/* HISTORY */
/* */
/* Revision 1.00 */
/* 20th December 2009. Created by Richard Sikora from Texas Instruments */
/* code. The crystal on the USB board has been changed */
/* from an earlier release and therefore some register */
/* values below also needed to be modified. */
/* */
/*****************************************************************************/
/*
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include "usbstk5515.h"
#include "aic3204.h"
#include "stdio.h" // For printf();
/* ------------------------------------------------------------------------ *
* *
* AIC3204 Initialisation. *
* Initialise both the registers and I2S *
* *
* ------------------------------------------------------------------------ */
/* Setup: Line input. Fs = 48000 Hz */
void aic3204_init(void)
{
/* Configure Serial Bus */
// SYS_EXBUSSEL |= 0x1000; // Configure Serial bus 0 for I2S0
SYS_EXBUSSEL = 0x1000;
/* Configure AIC3204 */
/* AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 1, 1 ); // Reset codec
AIC3204_rset( 0, 1 ); // Point to page 1
AIC3204_rset( 1, 8 ); // Disable crude AVDD generation from DVDD
AIC3204_rset( 2, 1 ); // Enable Analog Blocks, use LDO power
AIC3204_rset( 0, 0 );*/
/* PLL and Clocks config and Power Up */
/* AIC3204_rset( 27, 0x1d ); // BCLK and WCLK is set as o/p to AIC3204(Master)
AIC3204_rset( 28, 0x00 ); // Data ofset = 0
AIC3204_rset( 4, 3 ); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
AIC3204_rset( 6, 8 ); // PLL setting: J=7
AIC3204_rset( 7, 15 ); // PLL setting: HI_BYTE(D)
AIC3204_rset( 8, 0xdc ); // PLL setting: LO_BYTE(D)
AIC3204_rset( 30, 0x88 ); // For 32 bit clocks per frame in Master mode ONLY
// BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
AIC3204_rset( 5, 0x91 ); //PLL setting: Power up PLL, P=1 and R=1
AIC3204_rset( 13, 0 ); // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling
AIC3204_rset( 14, 0x80 ); // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080
AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6
AIC3204_rset( 11, 0x82 ); // Power up NDAC and set NDAC value to 2
AIC3204_rset( 12, 0x87 ); // Power up MDAC and set MDAC value to 7
AIC3204_rset( 18, 0x87 ); // Power up NADC and set NADC value to 7
AIC3204_rset( 19, 0x82 ); // Power up MADC and set MADC value to 2*/
/* DAC ROUTING and Power Up */
/* AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 0x0c, 8 ); // LDAC AFIR routed to HPL
AIC3204_rset( 0x0d, 8 ); // RDAC AFIR routed to HPR
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 64, 2 ); // Left vol=right vol
AIC3204_rset( 65, 0 ); // Left DAC gain to 0dB VOL; Right tracks Left
AIC3204_rset( 63, 0xd4 ); // Power up left,right data paths and set channel
AIC3204_rset( 0, 1 ); // Select page 1
AIC3204_rset( 0x10, 0x00 ); // Unmute HPL , 10dB gain
AIC3204_rset( 0x11, 0x00 ); // Unmute HPR , 10dB gain
AIC3204_rset( 9, 0x30 ); // Power up HPL,HPR
AIC3204_rset( 0, 0 ); // Select page 0
USBSTK5515_wait( 100 ); // wait*/
/* ADC ROUTING and Power Up */
// AIC3204_rset( 0, 1 ); // Select page 1
// AIC3204_rset( 51, 0x48); // power up MICBIAS
// LDOIN (0x48); //MM add mic bias
/* AIC3204_rset( 0x34, 0x30 );// STEREO 1 Jack
// IN2_L to LADC_P through 40 kohm
AIC3204_rset( 0x37, 0x30 );// IN2_R to RADC_P through 40 kohmm
AIC3204_rset( 0x36, 3 ); // CM_1 (common mode) to LADC_M through 40 kohm
AIC3204_rset( 0x39, 0xc0 );// CM_1 (common mode) to RADC_M through 40 kohm
// AIC3204_rset( 0x3b, 0 ); // MIC_PGA_L unmute
// AIC3204_rset( 0x3c, 0 ); // MIC_PGA_R unmute
AIC3204_rset( 59, 0x3c); // Unmute Left MICPGA, Gain = 30dB
AIC3204_rset( 60, 0x3c); // Unmute Right MICPGA, Gain = 30dB
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 0x51, 0xc0 );// Powerup Left and Right ADC
AIC3204_rset( 0x52, 0 ); // Unmute Left and Right ADC
AIC3204_rset( 0, 0 );
USBSTK5515_wait( 100 ); // Wait */
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 1, 0x01 ); // Reset codec
USBSTK5515_wait( 100 ); // Wait 1ms after reset
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 1, 0x08 ); // Disable crude AVDD generation from DVDD
AIC3204_rset( 2, 0x01 ); // Enable Analog Blocks, use LDO power
AIC3204_rset( 123,0x05 ); // Force reference to power up in 40ms
USBSTK5515_wait( 100 );// Wait at least 40ms
AIC3204_rset( 0, 0x00 ); // Select page 0
/* PLL and Clocks config and Power Up */
AIC3204_rset( 27, 0x0d );
AIC3204_rset( 27, 0x3d ); // BCLK and WCLK are set as o/p; AIC3204(Master)
AIC3204_rset( 28, 0x00 ); // Data ofset = 0
AIC3204_rset( 4, 0x03 ); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
AIC3204_rset( 6, 0x07 ); // PLL setting: J=7
AIC3204_rset( 7, 0x06 ); // PLL setting: HI_BYTE(D=1680)
AIC3204_rset( 8, 0x90 ); // PLL setting: LO_BYTE(D=1680)
AIC3204_rset( 30, 0x88 ); // For 32 bit clocks per frame in Master mode ONLY
// BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
AIC3204_rset( 5, 0x91 ); // PLL setting: Power up PLL, P=1 and R=1
USBSTK5515_wait( 100 ); // Wait for PLL to come up
AIC3204_rset( 13, 0x00 ); // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling
AIC3204_rset( 14, 0x80 ); // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080
AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6
AIC3204_rset( 11, 0x82 ); // Power up NDAC and set NDAC value to 2
AIC3204_rset( 12, 0x87 ); // Power up MDAC and set MDAC value to 7
AIC3204_rset( 18, 0x87 ); // Power up NADC and set NADC value to 7
AIC3204_rset( 19, 0x82 ); // Power up MADC and set MADC value to 2
/* DAC ROUTING and Power Up */
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 12, 0x08 ); // LDAC AFIR routed to HPL
AIC3204_rset( 13, 0x08 ); // RDAC AFIR routed to HPR
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 64, 0x02 ); // Left vol=right vol
AIC3204_rset( 65, 0x00 ); // Left DAC gain to 0dB VOL; Right tracks Left
AIC3204_rset( 63, 0xd4 ); // Power up left,right data paths and set channel
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 16, 0x00 ); // Unmute HPL , 0dB gain
AIC3204_rset( 17, 0x00 ); // Unmute HPR , 0dB gain
AIC3204_rset( 9 , 0x30 ); // Power up HPL,HPR
USBSTK5515_wait( 100 ); // Wait
/* ADC ROUTING and Power Up */
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 51, 0x48); // power up MICBIAS
AIC3204_rset( 52, 0x30 ); // STEREO 1 Jack
// IN2_L to LADC_P through 40 kohm
AIC3204_rset( 55, 0x30 ); // IN2_R to RADC_P through 40 kohmm
AIC3204_rset( 54, 0x03 ); // CM_1 (common mode) to LADC_M through 40 kohm
AIC3204_rset( 57, 0xc0 ); // CM_1 (common mode) to RADC_M through 40 kohm
// AIC3204_rset( 59, 0x00 ); // MIC_PGA_L unmute
//AIC3204_rset( 60, 0x00 ); // MIC_PGA_R unmute
// AIC3204_rset( 59, 0x3c); // Unmute Left MICPGA, Gain = 30dB
// AIC3204_rset( 60, 0x3c);
AIC3204_rset( 59, 60);
AIC3204_rset( 60, 60); // Unmute Right MICPGA, Gain = 30dB
AIC3204_rset( 82, 0x52 );
AIC3204_rset( 92, 0x5c );
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 81, 0xc0 ); // Powerup Left and Right ADC
// AIC3204_rset( 82, 0x00 ); // Unmute Left and Right ADC
AIC3204_rset( 0, 0x00 ); // Select page 0
USBSTK5515_wait( 100 ); // Wait
/* I2S settings */
I2S2_SRGR = 0x0;
I2S2_CR = 0x8010; // 16-bit word, slave, enable I2C
I2S2_ICMR = 0x3f; // Enable interrupts
}
/* ------------------------------------------------------------------------ *
* *
* AIC3204 Initialisation of both sampling frequency and gain in dB. *
* Initialise both the registers and I2S *
* *
* ------------------------------------------------------------------------ */
unsigned long set_sampling_frequency_and_gain(unsigned long SamplingFrequency, unsigned int ADCgain)
{
unsigned int PLLPR = 0x91; // Default to 48000 Hz
unsigned int gain;
unsigned long output;
if ( ADCgain >= 48)
{
gain = 95; // Limit gain to 47.5 dB
ADCgain = 48; // For display using printf()
}
else
{
gain = (ADCgain << 1); // Convert 1dB steps to 0.5dB steps
}
switch (SamplingFrequency)
{
case 48000:
PLLPR = 0x91; // 1001 0001b. PLL on. P = 1, R = 1.
printf("Sampling frequency 48000 Hz Gain = %2d dB\n", ADCgain);
output = 48000;
break;
case 24000:
PLLPR = 0xA1; // 1010 0001b. PLL on. P = 2, R = 1.
printf("Sampling frequency 24000 Hz Gain = %2d dB\n", ADCgain);
output = 24000;
break;
case 16000:
PLLPR = 0xB1; // 1011 0001b. PLL on. P = 3, R = 1.
printf("Sampling frequency 16000 Hz Gain = %2d dB\n", ADCgain);
output = 16000;
break;
case 12000:
PLLPR = 0xC1; //1100 0001b. PLL on. P = 4, R = 1.
printf("Sampling frequency 12000 Hz Gain = %2d dB\n", ADCgain);
output = 12000;
break;
case 9600:
PLLPR = 0xD1; //1101 0001b. PLL on. P = 5, R = 1.
printf("Sampling frequency 9600 Hz Gain = %2d dB\n", ADCgain);
output = 9600;
break;
case 8000:
PLLPR = 0xE1; //1110 0001b. PLL on. P = 6, R = 1.
printf("Sampling frequency 8000 Hz Gain = %2d dB\n", ADCgain);
output = 8000;
break;
case 6857:
PLLPR = 0xF1; //1111 0001b. PLL on. P = 7, R = 1.
printf("Sampling frequency 6857 Hz Gain = %2d dB\n", ADCgain);
output = 6857;
break;
default:
PLLPR = 0x91; // 1001 0001b. PLL on. P = 1, R = 1.
printf("Sampling frequency not recognised. Default to 48000 Hz Gain = %2d dB\n", ADCgain);
output = 48000;
break;
}
/* Configure Serial Bus */
// SYS_EXBUSSEL |= 0x1000; // Configure Serial bus 0 for I2S0
SYS_EXBUSSEL = 0x1000;
/* Configure AIC3204 */
/* AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 1, 1 ); // Reset codec
AIC3204_rset( 0, 1 ); // Point to page 1
AIC3204_rset( 1, 8 ); // Disable crude AVDD generation from DVDD
AIC3204_rset( 2, 1 ); // Enable Analog Blocks, use LDO power
AIC3204_rset( 0, 0 ); */
/* PLL and Clocks config and Power Up */
/* AIC3204_rset( 27, 0x1d ); // BCLK and WCLK is set as o/p to AIC3204(Master)
AIC3204_rset( 28, 0x00 ); // Data ofset = 0
AIC3204_rset( 4, 3 ); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
AIC3204_rset( 6, 7 ); // PLL setting: J=7
AIC3204_rset( 7, 0x06 ); // PLL setting: HI_BYTE(D)
AIC3204_rset( 8, 0x90 ); // PLL setting: LO_BYTE(D)
AIC3204_rset( 30, 0x88 ); // For 32 bit clocks per frame in Master mode ONLY
// BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
AIC3204_rset( 5, PLLPR ); //PLL setting: Power up PLL, P=1 and R=1
AIC3204_rset( 13, 0 ); // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling
AIC3204_rset( 14, 0x80 ); // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080
AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6
AIC3204_rset( 11, 0x87 ); // Power up NDAC and set NDAC value to 7
AIC3204_rset( 12, 0x82 ); // Power up MDAC and set MDAC value to 2
AIC3204_rset( 18, 0x87 ); // Power up NADC and set NADC value to 7
AIC3204_rset( 19, 0x82 ); // Power up MADC and set MADC value to 2*/
/* DAC ROUTING and Power Up */
/* AIC3204_rset( 0, 1 ); // Select page 1
AIC3204_rset( 0x0c, 8 ); // LDAC AFIR routed to HPL
AIC3204_rset( 0x0d, 8 ); // RDAC AFIR routed to HPR
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 64, 2 ); // Left vol=right vol
AIC3204_rset( 65, 0 ); // Left DAC gain to 0dB VOL; Right tracks Left
AIC3204_rset( 63, 0xd4 ); // Power up left,right data paths and set channel
AIC3204_rset( 0, 1 ); // Select page 1
AIC3204_rset( 0x10, 10 ); // Unmute HPL , 10dB gain
AIC3204_rset( 0x11, 10 ); // Unmute HPR , 10dB gain
AIC3204_rset( 9, 0x30 ); // Power up HPL,HPR
AIC3204_rset( 0, 0 ); // Select page 0
USBSTK5515_wait( 100 ); // wait*/
/* ADC ROUTING and Power Up */
// AIC3204_rset( 0, 1 ); // Select page 1
//AIC3204_rset( 51, 0x48); // power up MICBIAS
// LDOIN (0x48); //MM add mic bias
/* AIC3204_rset( 0x34, 0x10 );// STEREO 1 Jack
// IN2_L to LADC_P through 0 kohm
AIC3204_rset( 0x37, 0x10 );// IN2_R to RADC_P through 0 kohmm
AIC3204_rset( 0x36, 1 ); // CM_1 (common mode) to LADC_M through 0 kohm
AIC3204_rset( 0x39, 0x40 );// CM_1 (common mode) to RADC_M through 0 kohm
// AIC3204_rset( 0x3b, gain ); // MIC_PGA_L unmute
//AIC3204_rset( 0x3c, gain ); // MIC_PGA_R unmute
AIC3204_rset( 59, 0x3c); // Unmute Left MICPGA, Gain = 30dB
AIC3204_rset( 60, 0x3c); // Unmute Right MICPGA, Gain = 30dB
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 0x51, 0xc0 );// Powerup Left and Right ADC
AIC3204_rset( 0x52, 0 ); // Unmute Left and Right ADC
AIC3204_rset( 0, 0 );
USBSTK5515_wait( 100 ); // */
/* Configure AIC3204 */
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 1, 0x01 ); // Reset codec
USBSTK5515_wait( 100 ); // Wait 1ms after reset
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 1, 0x08 ); // Disable crude AVDD generation from DVDD
AIC3204_rset( 2, 0x01 ); // Enable Analog Blocks, use LDO power
AIC3204_rset( 123,0x05 ); // Force reference to power up in 40ms
USBSTK5515_wait( 100 );// Wait at least 40ms
AIC3204_rset( 0, 0x00 ); // Select page 0
/* PLL and Clocks config and Power Up */
AIC3204_rset( 27, 0x0d );
AIC3204_rset( 27, 0x3d );// BCLK and WCLK are set as o/p; AIC3204(Master)
AIC3204_rset( 28, 0x00 ); // Data ofset = 0
AIC3204_rset( 4, 0x03 ); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
AIC3204_rset( 6, 0x07 ); // PLL setting: J=7
AIC3204_rset( 7, 0x06 ); // PLL setting: HI_BYTE(D=1680)
AIC3204_rset( 8, 0x90 ); // PLL setting: LO_BYTE(D=1680)
AIC3204_rset( 30, 0x88 ); // For 32 bit clocks per frame in Master mode ONLY
// BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
AIC3204_rset( 5, PLLPR ); // PLL setting: Power up PLL, P=1 and R=1
USBSTK5515_wait( 100 ); // Wait for PLL to come up
AIC3204_rset( 13, 0x00 ); // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling
AIC3204_rset( 14, 0x80 ); // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080
AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6
AIC3204_rset( 11, 0x82 ); // Power up NDAC and set NDAC value to 2
AIC3204_rset( 12, 0x87 ); // Power up MDAC and set MDAC value to 7
AIC3204_rset( 18, 0x87 ); // Power up NADC and set NADC value to 7
AIC3204_rset( 19, 0x82 ); // Power up MADC and set MADC value to 2
/* DAC ROUTING and Power Up */
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 12, 0x08 ); // LDAC AFIR routed to HPL
AIC3204_rset( 13, 0x08 ); // RDAC AFIR routed to HPR
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 64, 0x02 ); // Left vol=right vol
AIC3204_rset( 65, 0x00 ); // Left DAC gain to 0dB VOL; Right tracks Left
AIC3204_rset( 63, 0xd4 ); // Power up left,right data paths and set channel
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 16, 0x00 ); // Unmute HPL , 0dB gain
AIC3204_rset( 17, 0x00 ); // Unmute HPR , 0dB gain
AIC3204_rset( 9 , 0x30 ); // Power up HPL,HPR
USBSTK5515_wait( 100 ); // Wait
/* ADC ROUTING and Power Up */
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 51, 0x48); // power up MICBIAS
AIC3204_rset( 52, 0x30 ); // STEREO 1 Jack
// IN2_L to LADC_P through 40 kohm
AIC3204_rset( 55, 0x10 ); // IN2_R to RADC_P through 40 kohmm
AIC3204_rset( 54, 0x01 ); // CM_1 (common mode) to LADC_M through 40 kohm
AIC3204_rset( 57, 0x40 ); // CM_1 (common mode) to RADC_M through 40 kohm
// AIC3204_rset( 59, 0x00 ); // MIC_PGA_L unmute
//AIC3204_rset( 60, 0x00 ); // MIC_PGA_R unmute
AIC3204_rset( 59, gain); // Unmute Left MICPGA, Gain = 30dB
AIC3204_rset( 60, gain); // Unmute Right MICPGA, Gain = 30dB
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 82, 0x52 );
AIC3204_rset( 92, 0x5c );
AIC3204_rset( 81, 0xc0 ); // Powerup Left and Right ADC
// AIC3204_rset( 82, 0x00 ); // Unmute Left and Right ADC
AIC3204_rset( 0, 0x00 ); // Select page 0
USBSTK5515_wait( 100 ); // Wait
/* I2S settings */
I2S2_SRGR = 0x0;
I2S2_CR = 0x8010; // 16-bit word, slave, enable I2C
I2S2_ICMR = 0x3f; // Enable interrupts
return(output);
}
/* ------------------------------------------------------------------------ *
* *
* End of aic3204_init.c *
* *
* ------------------------------------------------------------------------ */
Hi,
Please provide the i2cdump when it's running so we can check what's actually written to the device.
What's the MCLK frequency?
Regards.
HI pdjuandi
These is my I2C application code
USBSTKT2C.c:
*
* I2C implementation
*
*/
#include "usbstk5515_i2c.h"
#include "usbstk5515_gpio.h"
static Int32 i2c_timeout = 0x0fff;
/* ------------------------------------------------------------------------ *
* *
* _I2C_init( ) *
* *
* Enable and initalize the I2C module *
* The I2C clk is set to run at 20 KHz *
* *
* ------------------------------------------------------------------------ */
Int16 USBSTK5515_I2C_init( )
{
I2C_MDR = 0x0400; // Reset I2C
I2C_PSC = 15; // Config prescaler for 100MHz
I2C_CLKL = 25; // Config clk LOW for 100kHz
I2C_CLKH = 25; // Config clk HIGH for 100kHz
I2C_MDR = 0x0420 ; // Release from reset; Master, Transmitter, 7-bit address
return 0;
}
/* ------------------------------------------------------------------------ *
* *
* _I2C_close( ) *
* *
* ------------------------------------------------------------------------ */
Int16 USBSTK5515_I2C_close( )
{
I2C_MDR = 0; // Reset I2C
return 0;
}
/* ------------------------------------------------------------------------ *
* *
* _I2C_reset( ) *
* *
* ------------------------------------------------------------------------ */
Int16 USBSTK5515_I2C_reset( )
{
USBSTK5515_I2C_close( );
USBSTK5515_I2C_init( );
return 0;
}
/* ------------------------------------------------------------------------ *
* *
* _I2C_write( i2c_addr, data, len ) *
* *
* I2C write in Master mode *
* *
* i2c_addr <- I2C slave address *
* data <- I2C data ptr *
* len <- # of bytes to write *
* *
* ------------------------------------------------------------------------ */
Int16 USBSTK5515_I2C_write( Uint16 i2c_addr, Uint8* data, Uint16 len )
{
Int16 timeout, i;
//I2C_IER = 0x0000;
I2C_CNT = len; // Set length
I2C_SAR = i2c_addr; // Set I2C slave address
I2C_MDR = MDR_STT // Set for Master Write
| MDR_TRX
| MDR_MST
| MDR_IRS
| MDR_FREE;
USBSTK5515_wait(100); // Short delay
for ( i = 0 ; i < len ; i++ )
{
I2C_DXR = data[i]; // Write
timeout = 0x510; // I2C_timeout = 1ms;
USBSTK5515_GPIO_setOutput( 17, 1);
do
{
if ( timeout-- < 0 )
{
USBSTK5515_GPIO_setOutput( 17, 0);
USBSTK5515_I2C_reset( );
return -1;
}
} while ( ( I2C_STR & STR_XRDY ) == 0 );// Wait for Tx Ready
}
I2C_MDR |= MDR_STP; // Generate STOP
USBSTK5515_waitusec(1000);
return 0;
}
/* ------------------------------------------------------------------------ *
* *
* _I2C_read( i2c_addr, data, len ) *
* *
* I2C read in Master mode *
* *
* i2c_addr <- I2C slave address *
* data <- I2C data ptr *
* len <- # of bytes to write *
* *
* Returns: 0: PASS *
* -1: FAIL Timeout *
* *
* ------------------------------------------------------------------------ */
Int16 USBSTK5515_I2C_read( Uint16 i2c_addr, Uint8* data, Uint16 len )
{
Int32 timeout, i;
I2C_CNT = len; // Set length
I2C_SAR = i2c_addr; // Set I2C slave address
I2C_MDR = MDR_STT // Set for Master Read
| MDR_MST
| MDR_IRS
| MDR_FREE;
USBSTK5515_wait( 10 ); // Short delay
for ( i = 0 ; i < len ; i++ )
{
timeout = i2c_timeout;
//Wait for Rx Ready
do
{
if ( timeout-- < 0 )
{
USBSTK5515_I2C_reset( );
return -1;
}
} while ( ( I2C_STR & STR_RRDY ) == 0 );// Wait for Rx Ready
data[i] = I2C_DRR; // Read
}
I2C_MDR |= MDR_STP; // Generate STOP
USBSTK5515_waitusec(10);
return 0;
}
AIC3204.c :
/*****************************************************************************/
/* */
/* FILENAME */
/* aic3204.c */
/* */
/* DESCRIPTION */
/* Setup functions for aic3204 codec on the TMS320C5505 USB Stick. */
/* */
/* REVISION */
/* Revision: 1.00 */
/* Author : Richard Sikora */
/*---------------------------------------------------------------------------*/
/* */
/* HISTORY */
/* */
/* Revision 1.00 */
/* 20th December 2009. Created by Richard Sikora from Spectrum Digital */
/* code. Created new functions for codec read */
/* and write. */
/* */
/*****************************************************************************/
/*
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include "stdio.h"
#include "usbstk5515.h"
#include "aic3204.h"
#include "usbstk5515_gpio.h"
#include "usbstk5515_i2c.h"
Int16 counter1; // Counters for monitoring real-time operation.
Int16 counter2;
/* ------------------------------------------------------------------------ *
* *
* _AIC3204_rget( regnum, regval ) *
* *
* Return value of codec register regnum *
* *
* ------------------------------------------------------------------------ */
Int16 AIC3204_rget( Uint16 regnum, Uint16* regval )
{
Int16 retcode = 0;
Uint8 cmd[2];
cmd[0] = regnum & 0x007F; // 7-bit Device Address
cmd[1] = 0;
retcode |= USBSTK5515_I2C_write( AIC3204_I2C_ADDR, cmd, 1 );
retcode |= USBSTK5515_I2C_read( AIC3204_I2C_ADDR, cmd, 1 );
*regval = cmd[0];
USBSTK5515_wait( 10 );
return retcode;
}
/* ------------------------------------------------------------------------ *
* *
* _AIC3204_rset( regnum, regval ) *
* *
* Set codec register regnum to value regval *
* *
* ------------------------------------------------------------------------ */
Int16 AIC3204_rset( Uint16 regnum, Uint16 regval )
{
Uint8 cmd[2];
cmd[0] = regnum & 0x007F; // 7-bit Device Address
cmd[1] = regval; // 8-bit Register Data
return USBSTK5515_I2C_write( AIC3204_I2C_ADDR, cmd, 2 );
}
/* ------------------------------------------------------------------------ *
* *
* aic3204_enable( ) *
* *
* ------------------------------------------------------------------------ */
void aic3204_hardware_init(void)
{
//SYS_EXBUSSEL |= 0x0020; // Select A20/GPIO26 as GPIO26
SYS_EXBUSSEL = 0x0020; // Select A20/GPIO26 as GPIO26
USBSTK5515_GPIO_init();
USBSTK5515_GPIO_setDirection(GPIO26, GPIO_OUT);
USBSTK5515_GPIO_setOutput( GPIO26, 1 ); // Take AIC3204 chip out of reset
USBSTK5515_I2C_init( ); // Initialize I2C
USBSTK5515_wait( 100 ); // Wait
}
/* ------------------------------------------------------------------------ *
* *
* aic3204_disable( ) *
* *
* ------------------------------------------------------------------------ */
void aic3204_disable(void)
{
AIC3204_rset( 1, 1 ); // Reset codec
USBSTK5515_GPIO_setOutput( GPIO26, 0 ); // Put AIC3204 into reset
I2S2_CR = 0x00;
}
/* ------------------------------------------------------------------------ *
* *
* aic3204_codec_read( ) *
* *
* ------------------------------------------------------------------------ */
void aic3204_codec_read(Int16* left_input, Int16* right_input)
{
volatile Int16 dummy;
counter1 = 0;
printf("\n\nRead Digital audio inputs\n");
/* Read Digital audio inputs */
while(!(I2S2_IR & RcvR) )
{
counter1++; // Wait for receive interrupt
}
printf("\n\nAudio Received\n");
*left_input = I2S2_W0_MSW_R; // Read Most Significant Word of first channel
dummy = I2S2_W0_LSW_R; // Read Least Significant Word (ignore)
*right_input = I2S2_W1_MSW_R; // Read Most Significant Word of second channel
dummy = I2S2_W1_LSW_R; // Read Least Significant Word of second channel (ignore)
}
/* ------------------------------------------------------------------------ *
* *
* aic3204_codec_write( ) *
* *
* ------------------------------------------------------------------------ */
void aic3204_codec_write(Int16 left_output, Int16 right_output)
{
counter2 = 0;
while( !(I2S2_IR & XmitR) )
{
counter2++; // Wait for transmit interrupt
}
I2S2_W0_MSW_W = left_output; // Left output
I2S2_W0_LSW_W = 0;
I2S2_W1_MSW_W = right_output; // Right output
I2S2_W1_LSW_W = 0;
}
/* ------------------------------------------------------------------------ *
* *
* End of aic3204.c *
* *
* ------------------------------------------------------------------------ */
I am new to TMS20C5535 ezdsp board
I don't know where it is use MLCK Frequency but This is my PLL.C file
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2008
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** @file csl_pll_example.c
*
* @brief PLL functional layer sample source file
*
*
* \page page12 CSL PLL EXAMPLE DOCUMENTATION
*
* \section PLL PLL EXAMPLE
*
* \subsection PLLx TEST DESCRIPTION:
* This test code verifies the functionality of CSL PLL module. PLL module
* on the C5505/C5515 DSP is used to generate clock for CPU and peripherals.
* A 32KHz input clock is supplied to the PLL using which different system clock
* values are generated. Different system clock values are generated by
* configuring the PLL to different divider values.
*
* During the test PLL module will be configured to the 60MHz clock frequency
* using PLL_config() API. Configured values are read back and verified using
* PLL_getConfig() APIs. All the values should match the configured values
* except the test lock mon value which will reflect on the registers only
* after the PLL is up. Values read from the PLL are displayed on the CCS
* "stdout" window. Manual inspection is required to verify the test success.
*
* C5515 DSP PLL register bit fileds are little different than that of C5505 DSP.
* Use the 'PLL_Config' values defined 12.288MHz - 120MHz to verify PLL
* configuration.
*
* NOTE: THIS TEST HAS BEEN DEVELOPED TO WORK WITH CHIP VERSIONS C5505 AND
* C5515. MAKE SURE THAT PROPER CHIP VERSION MACRO CHIP_5505/CHIP_5515 IS
* DEFINED IN THE FILE c55xx_csl\inc\csl_general.h.
*
* \subsection PLLy TEST PROCEDURE:
* @li Open the CCS and connect the target (C5505/C5515 EVM)
* @li Open the project "CSL_PLL_Example.pjt" and build it
* @li Load the program on to the target
* @li Run the program and observe the test result
* @li Repeat the test in Release mode
*
* \subsection PLLz TEST RESULT:
* @li All the CSL APIs should return success
* @li Configuration values read from the PLL should match with the actual
* configured values except the test lock mon value.
*
*/
/* ============================================================================
* Revision History
* ================
* 15-Sept-2008 Created
*
* 18-May-2010. Modified by Richard Sikora for adjustable PLL.
*
* 20-Aug-2010. Added 1 MHz, 2 MHz, 12 MHz and 98 MHz for 5515.
*
* 16-Oct-2010. Added # if defined CHIP_C5505_C5515
*
* ============================================================================
*/
#include<stdio.h>
#include "csl_pll.h"
#include "csl_general.h"
#include "csl_pllAux.h"
PLL_Obj pllObj;
PLL_Config pllCfg1;
PLL_Handle hPll;
#if ((defined(CHIP_5505)) || (defined(CHIP_5515)) || (defined(CHIP_C5505_C5515)) )
PLL_Config pllCfg_1MHz = {0x8895, 0x8000, 0x0806, 0x0247};
PLL_Config pllCfg_2MHz = {0x8895, 0x8000, 0x0806, 0x0223};
PLL_Config pllCfg_12MHz = {0x8895, 0x8000, 0x0806, 0x0205};
PLL_Config pllCfg_12p288MHz = {0x8173, 0x8000, 0x0806, 0x0000};
PLL_Config pllCfg_40MHz = {0x8E4A, 0x8000, 0x0806, 0x0202};
PLL_Config pllCfg_60MHz = {0x8724, 0x8000, 0x0806, 0x0000};
PLL_Config pllCfg_75MHz = {0x88ED, 0x8000, 0x0806, 0x0000};
PLL_Config pllCfg_98MHz = {0x8BAB, 0x8000, 0x0806, 0x0000};
PLL_Config pllCfg_100MHz = {0x8BE8, 0x8000, 0x0806, 0x0000};
PLL_Config pllCfg_120MHz = {0x8E4A, 0x8000, 0x0806, 0x0000};
#else
// Order of registers is PLL_CNTRL1, PLL_CNTRL_2, PLL_CNTRL3, PLL_CNTRL_4
PLL_Config pllCfg_1MHz = {0x82DB, 0x0000, 0x0806, 0x0208};
PLL_Config pllCfg_2MHz = {0x82DB, 0x0000, 0x0806, 0x0202};
PLL_Config pllCfg_12MHz = {0x82EB, 0x8000, 0x0806, 0x0200};
PLL_Config pllCfg_12p288MHz = {0x82ED, 0x8000, 0x0806, 0x0200};
PLL_Config pllCfg_40MHz = {0x8262, 0x8000, 0x0806, 0x0300};
PLL_Config pllCfg_60MHz = {0x81C8, 0xB000, 0x0806, 0x0000};
PLL_Config pllCfg_75MHz = {0x823B, 0x9000, 0x0806, 0x0000};
PLL_Config pllCfg_98MHz = {0x82ED, 0x8000, 0x0806, 0x0000};
PLL_Config pllCfg_100MHz = {0x82FA, 0x8000, 0x0806, 0x0000};
PLL_Config pllCfg_120MHz = {0x8392, 0xA000, 0x0806, 0x0000};
#endif
PLL_Config *pConfigInfo;
#define CSL_TEST_FAILED (1)
#define CSL_TEST_PASSED (0)
int pll_frequency_setup(unsigned int frequency)
{
CSL_Status status;
status = PLL_init(&pllObj, CSL_PLL_INST_0);
if(CSL_SOK != status)
{
printf("PLL init failed \n");
return (status);
}
hPll = (PLL_Handle)(&pllObj);
PLL_reset(hPll);
/* Configure the PLL for different frequencies */
if ( frequency == 1)
{
pConfigInfo = &pllCfg_1MHz;
printf("\nLL frequency 1 MHz\n");
}
else if ( frequency == 2)
{
pConfigInfo = &pllCfg_2MHz;
printf("\nPLL frequency 2 MHz\n");
}
else if ( frequency == 12)
{
pConfigInfo = &pllCfg_12MHz;
printf("\nPLL frequency 12 MHz\n");
}
else if ( frequency == 40)
{
pConfigInfo = &pllCfg_40MHz;
printf("\nPLL frequency 40 MHz\n");
}
else if ( frequency == 60)
{
pConfigInfo = &pllCfg_60MHz;
printf("\nPLL frequency 60 MHz\n");
}
else if ( frequency == 75)
{
pConfigInfo = &pllCfg_75MHz;
printf("\nPLL frequency 75 MHz\n");
}
else if ( frequency == 98)
{
pConfigInfo = &pllCfg_98MHz;
printf("\nPLL frequency 98 MHz\n");
}
else if ( frequency == 120)
{
pConfigInfo = &pllCfg_120MHz;
printf("\nPLL frequency 120 MHz\n");
}
else
{
pConfigInfo = &pllCfg_100MHz;
printf("\nPLL frequency 100 MHz\n");
}
status = PLL_config (hPll, pConfigInfo);
if(CSL_SOK != status)
{
printf("PLL config failed\n");
return(status);
}
status = PLL_getConfig(hPll, &pllCfg1);
if(status != CSL_SOK)
{
printf("TEST FAILED: PLL get config... Failed.\n");
printf ("Reason: PLL_getConfig failed. [status = 0x%x].\n", status);
return(status);
}
printf("REGISTER --- CONFIG VALUES\n");
printf("PLL_CNTRL1 %04x --- %04x\n",pllCfg1.PLLCNTL1,hPll->pllConfig->PLLCNTL1);
printf("PLL_CNTRL2 %04x --- %04x Test Lock Mon will get set after PLL is up\n",
pllCfg1.PLLCNTL2,hPll->pllConfig->PLLCNTL2);
printf("PLL_CNTRL3 %04x --- %04x\n",pllCfg1.PLLINCNTL,hPll->pllConfig->PLLINCNTL);
printf("PLL_CNTRL4 %04x --- %04x\n",pllCfg1.PLLOUTCNTL,hPll->pllConfig->PLLOUTCNTL);
status = PLL_bypass(hPll);
if(CSL_SOK != status)
{
printf("PLL bypass failed:%d\n",CSL_ESYS_BADHANDLE);
return(status);
}
status = PLL_enable(hPll);
if(CSL_SOK != status)
{
printf("PLL enable failed:%d\n",CSL_ESYS_BADHANDLE);
return(status);
}
return(CSL_TEST_PASSED);
}
/********************************************************************************************/
/* */
/* End of PLL.c */
/* */
/********************************************************************************************/
Hi,
I need the i2cdump and not the application code as this can be over-written.
I want to see what's actually written to the device.
What's the MCLK frequency you are running with?
Regards.