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TLV320AIC3204: Beep Generation

Alexander Shapirshtein
Prodigy 40 points
Part Number: TLV320AIC3204

Hello,

 

My task is implementation of audio capability in our project, which is based on i.MX6 processor (ARM).

The sound is generated by playing WAV-files: the data is passed via AUDMUX-SSI interface to CODEC TLV320AIC3204.

At the first step, it was verified that the I2S signal (clock and data) outputs from i.MX6 to CODEC, and signal was correct.

At second step, we wanted to be sure that connection between CODEC and headset is correct. For that I’ve tried to activate the internal BEEP signal on CODEC. I prepared the configuration sequence in accordance with recommendations in §5.14.1 Beep Generation (see “TLV320AIC3204. Ultra Low Power Stereo Audio Codec. SLOS602A–September 2008”). The sequence I’ve attached below.

The issue is that I did not hear the BEEP after its starting (Page 0, Reg 71, D(7)=1) . And I did not detect that BEEP enabling has been automatically set back to 0 (Page 0, Reg 71, D(7)=0). It looks like something in BEEP activation was wrong.

Please, help me to solve this issue.

 

Beep Configuration sequence:

Reg#

Name                                                    

SetVal

ActVal (verification)

0

1

11

12

13

14

27

60

67

4

PAGE_SELECT-0             

SW_RESET                  

CLOCK SET NDAC            

CLOCK SET MDAC            

DAC OSR SET-1             

DAC OSR SET-2             

AUDIO IF SET-1            

DAC SIGNAL                

HEADSET DETECT: exp-0xB2  

CLOCK SET-1 

0x00 

0x00 

0x81 

0x82 

0x00 

0x80 

0x00 

0x19 

0x92 

0x00 

0x00

0x01

0x81

0x82

0x00

0x80

0x00

0x19

0x92

0x00

0

1

PAGE_SELECT-8             

DAC_ADPT_FLTR_ENABLE

0x08 

0x04

0x08

0x04

0

1

2

123

20

10

11

13

14

3

4

16

17

9

PAGE_SELECT-1             

POWER CONFIG              

LDO CTRL                  

REF POWRUP CNFG 

HEADPHONE STARTUP 

COMMON MODE 

OVER CURRENT

HPR ROUTE  

LOL ROUTE  

PLAYBACK-1

PLAYBACK-2

HPR GAIN-1

HPR GAIN-2

OUT DRV PWR CTRL

0x01 

0x08

0x00

0x01

0x25

0x33

0x00

0x08

0x08

0x00

0x00

0x00

0x00

0x30

0x01

0x08

0x00

0x01

0x25

0x33

0x00

0x08

0x08

0x00

0x00

0x00

0x00

0x30

    WAIT 2.5 secs             2500

 

 

0

63

64

73

74

75

76

77

78

79

72

71

PAGE_SELECT-0

DAC CHN SET-1

DAC CHN UNMUTE

BEEP LENGTH:23-16

BEEP LENGTH:15-8

BEEP LENGTH:7-0

BEEP GEN6.SIN(15:8)

BEEP GEN7.SIN(7:0)

BEEP GEN8.COS(15:8)

BEEP GEN9.COS(7:0)

BEEP CH_RT                

BEEP CH_LT+ENABLE

0x00 

0xD4 

0x02 

0x00 

0x17 

0x70 

0x10 

0xD8 

0x7E 

0xE3 

0x80 

0x80

0x00 

0xD4 

0x02 

0x00 

0x17 

0x70 

0x10 

0xD8 

0x7E 

0xE3 

0x80 

0x80

 

 

Thank you in advance.

 

  • 0
    TI__Mastermind 30210 points
    Alexander,

    I first looked over your configuration and nothing seemed odd, so I transcribed your configuration into the format the GUI for the EVM understands and when I load this configuration using our EVM, I get a beep.

    do you have a schematic I can see? or can you tell me more about your design?

    best regards,
    -steve Wilson
  • 0 in reply to Steve-Wilson
    Prodigy 40 points

    Fist of all, thank you for your help.

    It was positive to hear that my BEEP configuration is valid.

    As you ask me, I've attached the scheme of H/W.

    PS: That is my first time of usage this kind of communication (I'm talking about this support interface), and may be the scheme has been attached not so good. Keep me informed.

    CPVD_AUDIO_1.pdf

  • 0 in reply to Alexander Shapirshtein
    TI__Mastermind 30210 points
    Alexander,

    We resolved your issue behind the scenes via email, but I wanted to post the solution here for future users with a similar issue.

    The main problem with the beep was an issue of resource class.

    In Section 2.4.6 of the Datasheet the steps for setting up the DAC are detailed, of particular interest is the bit about resource classes. (MDAC*DOSR)/32 >= RC

    in your Case the MADC = 2 and DOSR is 128, which means this condition is violated. Currently your configuration only uses clock dividers, so we need to use the PLL in order to boost the Codec CLKIN frequency.

    for a MCLK of 11.55MHz (which you are using) the PLL configuration is below:

    # select page 0
    w 30 00 00

    # PLL Jvalue = 8
    w 30 06 08

    #PLL D-Value = 5112
    W 30 07 13 F7

    #PLL is powered up P=R=1
    w 30 05 91

    # CLKDIV input = PLL out
    w 30 19 03

    #CLOCK SET-1 (PLL OUT IS CODEC_CLKIN)
    w 30 04 43

    #CLOCK SET NDAC
    w 30 0b 82

    #CLOCK SET MDAC
    w 30 0C 88


    The second issue is with signal routing. The LOL_OUT was routed to instead of the HPL_OUT.

    # select page 1
    w 30 00 01

    #HPL_OUT CTRL
    w 30 12 80

    Those were the two issues we resolved.

    Best regards,
    -Steve Wilson