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TLV320AIC3110: The register setting, Output, Clock

Part Number: TLV320AIC3110
Other Parts Discussed in Thread: TLV320AIC3100

Tool/software:

Hi,

After inputting the sound source from MIC1LP/MIC1RP and confirming that the sound source is output from HPL/HPR/SPK1, I switch the sound source to I2S and check the sound output. Since there is no proper sound source, I am inputting the data which repeats H/L every WCLK cycle and assuming the sound output of about 10KHz, but the output as expected is not obtained → 3100_wave_1.png (CH1 (yellow); HPL CH2 (red): DIN CH3 (blue): WCLK)

1. Could you check the current register setting?

・Register surrounded by a black frame → Leave the initial value (reset release)
・Register surrounded by a red frame → Set with the initial value, but the set value may be changed if necessary
・Register(DESCRIPTION) surrounded by a red frame → Change and set
・Register surrounded by a blue frame → Set with analog audio input

Page 1/Register 35 was set to the blue frame and others to the red frame, and it was confirmed that the audio input from MIC1LP/MIC1RP was output to HPL/HPR. Then, Page 1/Register 35 was set to the red frame, and it was confirmed that the input I2S sound source was output, but it was not the expected audio.

TLV320AIC3100(registor setting)1018.pdf

2. WCLK is 21.701KHz, while MCLK is 256 times WCLK, or 5.555456 MHz. BCLK is 32 times WCKL, or 69.4432KHz. Is this setting OK?

Best Regards,

Nishie

  • Hi Nishie-san,

    Could you attach the commands you are using or a register dump? Following the pdf with the colors is confusing and some of the registers need to be set in a specific order. I don't see what you set the PLL settings to.

    Also, what is the output that is incorrect? Do you expect the output to look like the yellow wave from your oscilloscope but it is actually the green and you get no output? Or am I misinterpreting?

    Let me know about this info and we can solve this!

    Best,
    Mir

  • Hi Mir-san,

    Thank you for your support.

    I wrote the register setting procedure in an Excel file. Is this file OK?

    register setting procedure.xlsx

    I will send the waveform again. (CH2 (red): HPL CH3 (blue): DIN CH4 (green): WCLK)

    The output is a red waveform (HPL). Since we input data on a scale of 12 bits, we assumed an output of 3.3Vp-p at 1 kHz at peak FFFH, but in reality, it was 100mVp-p as shown in the attached waveform.

    If I can't find the cause just by register setting, I would like to send you a circuit diagram via private message. I would appreciate if you accept my friend request.

    2. WCLK is 21.701KHz, while MCLK is 256 times WCLK, or 5.555456 MHz. BCLK is 32 times WCKL, or 69.4432KHz. Is this setting OK? WCLK is set to 21.701 kHz, is there any problem?

    Best Regards,

    Nishie

  • Hi Nishie-san,

    Using the CodecControl software, I found some register writes that you would want to change and add. You should change your MDAC value, and add parameters for NADC and MADC. Here is the I2C writes for that:

    w 30 12 81 #ADC NADC_VAL set to 1
    w 30 13 82 #ADC MADC_VAL set to 2

    w 30 0b 81 #DAC NDAC_VAl set to 1
    w 30 0c 82 #DAC MDAC_VAL set to 2

    Also, 21.701kHz is a strange sample rate, and although I do not see any documentation saying certain sample rate are or are not allowed by the device, I would not be surprised if this sample rate is not supported. I cannot get my EVM to operate in slave mode, or I would test it, but see if setting these registers helps. 

    Also, what do you mean by input data at 12 bits? You have a 16bit audio interface, so it expects the data in 16 bit increments.

    Best,
    Mir

  • Hi Mi-san,

    I will check register settings and sample rate.

    Also, 12 bits of input data are data whose upper 4 bits are 0. I would like to review the input data and check the output data.

    Best Regards,

    Nishie

  • Ok, got it. Let me know what you find out.

    Best,
    Mir