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DRV595: Maximum slew rate for SDZ pin

Part Number: DRV595


Tool/software:

Hi alll,

According to the absolute maximum ratings in the datasheet, the maximum slew rate of the SDZ pin is 10V/ms, and if this is exceeded, a 100 KΩ series resistor is required.

The FPGA is running at 3.3V, and the DRV595's PVCC/AVCC are running at 24V.
A 100k-ohm resistor is inserted in series between the FPGA and SDZ.

When 0V and 3.3V signals are input from the FPGA to SDZ, the slew rate of the falling and rising waveforms at the SDZ pin was approximately 300V/ms, which is faster than the maximum slew rate of 10V/ms.
The slew rate measurement is based on the time change from 10% to 90% of the maximum voltage value.

Is there any problem with this observation result?

Regards,
Toshi

  • Hi Toshi,

    Do you mean the slew rate increased when adding the resistor in series? What is the slew rate before adding the resistor?
    The point of adding the resistor in series when slew rate is high, is basically just to limit the amount of current flowing to the pin.

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • IVAN-san,

    Thank you for your reply.

    Before connecting the 100k-ohm series resistor, a 75-ohm damping resistor was inserted.
    The rise slew rate was about 140kV/ms and the fall slew rate was 235kV/ms.

    The slew rate was about 300V/ms when the 100k-ohm series resistor was inserted instead of 75-ohm dumping resistor, so the slew rate was significantly lower.

    The customer's evaluation results are as above. Is there any problem?

    Thanks and regards,
    Toshi

  • Hi Toshi,

    The diagram looks good, in addition I think the SDz pin is only being pulled-up to 3.3V and not PVCC-24V, which is safer for the SDz pin anyways.

    Best regards,
    -Ivan Salazar
    Applications Engineer