Tool/software:
Hi alll,
According to the absolute maximum ratings in the datasheet, the maximum slew rate of the SDZ pin is 10V/ms, and if this is exceeded, a 100 KΩ series resistor is required.
The FPGA is running at 3.3V, and the DRV595's PVCC/AVCC are running at 24V.
A 100k-ohm resistor is inserted in series between the FPGA and SDZ.
When 0V and 3.3V signals are input from the FPGA to SDZ, the slew rate of the falling and rising waveforms at the SDZ pin was approximately 300V/ms, which is faster than the maximum slew rate of 10V/ms.
The slew rate measurement is based on the time change from 10% to 90% of the maximum voltage value.
Is there any problem with this observation result?
Regards,
Toshi
