• State
  • Locked Locked
  • Replies 5 replies
  • Subscribers 30 subscribers
  • Views 233 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

PCMD3180: Can this support audio signals of 1.8V input and give 3.3V output

PCMD3180: AREG max mA Available for External Misc. Circuits (beyond internal decimator load)

Chris Nielsen
Intellectual 605 points
Part Number: PCMD3180

Tool/software:

That is great news that the front-end (AVDD, actually digital decimation section, not analog) can run at 1.8V, and keep IOVDD at 3.3V [allows mics on flex to be low EMI at 1.8V, instead of antennas].

It appears that AREG (on-chip regulator) can be tied to AVDD and supply this 1.8V, true?

It then makes sense to power the PDM mics from the same supply as the decimator (1.8V I/O for all involved).

My main question is how much current can AREG (on-chip) supply?  I don't see it listed.  I plan to use 8 mics, totaling about 9 mA; can AREG handle this added load, in addition to its decimator responsibilities?  If at all possible, I'd prefer to know AREG max capability, as opposed to "the 8 mics should be ok", so I can get comfortable with the regulator margin.

Thank you, Chris

  • 0
    Intellectual 605 points

    Follow-up.  I'm going for the ultimate low noise, high-SNR PDM mic setup.  Since the on-chip circuitry connected to AVDD is all digital, isn't it likely to kick some of that digital noise back out to the caps on AVDD, then on to the PDM mics?  So, even if AREG has impressive low noise specs, it will be degraded or cancelled out by AVDD noise, right?  If you agree with the above, then placing a low cost, low noise LDO (3.3 to 1.8) feeding just the mics power inputs would be the best solution?  I'm hoping that AREG can still work well connected to AVDD (to avoid a 2nd LDO).  Thanks, Chris

  • 0 in reply to Chris Nielsen
    Intellectual 605 points

    My bad.  Pad 17 AREG description seems to imply that the on-chip regulator is generating 1.8V to the pad, but I misinterpreted it, as EVM board doesn't work if I assume that.  The only setup I've found that works is to let the 1.8V discrete LDO feed AVDD and tie it to AREG...and I connected PDM mics to AVDD.

  • 0 in reply to Chris Nielsen
    Intellectual 605 points

    Sorry for all the replies, but heavy in debug now and discovering.

    To try to get to just one 1.8V LDO (for the PDM mics, super low noise rail), can I tie AVDD to IOVDD (3.3V), which should then activate the on-chip 1.8V AREG, feeding the internal decimator logic?  Would this also set the PDM CLK & DAT1/2 logic levels to 1.8V? (avoiding the need for a 2nd 1.8V LDO to feed AVDD).

    My goal is 1.8V PDM mics (low EMI), 3.3V codec TDM I/O (my CPU requires 3.3V), and a minimum of hardware.  Thanks, Chris

  • 0 in reply to Chris Nielsen
    TI__Mastermind 27220 points

    Apologies for the delay, will update with response by friday

  • 0 in reply to Daveon Douglas
    TI__Mastermind 27220 points

    Hi Chris,

    There isn't a register setting to force PDM logic levels to 1.8V. The PDM logic will follow IOVDD. If you need a low-noise option than I would suggest an LDO or level shifter for the PDM interface.

    An external AREG supply is only recommended when AVDD is less than 1.98V. Otherwise, we suggest the 1.8V output be decoupled this to ground and not load additional circuitry. AREG needs to remain a stable 1.8V.

    AVDD and IOVDD can be tied together as a single supply:

    • Either 3.3V or 1.8V I recommend a ferrite bead between the two.
    • Use a single 1.8V supply for the entire system, tying 1.8V to AVDD, and using AVDD for the PDM circuitry.