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Original question:

PCM5102A: Schematic review

PCM5102A: The PCM5102A outputs nothing.

Rubin Chen
Intellectual 420 points
Part Number: PCM5102A

Tool/software:

LRCK=8kHz

BCK=8kHz*32bit*2=512kHz

SCK=1MHz

POWER is OK.

But we measure nothing at OUTL.

The attached diagram is a schematic diagram. Please help analyze possible causes of nothing measured at OUTL.

Thanks.

3480.audio_pcm5102a.pdf

  • 0
    TI__Mastermind 30781 points

    Hello,

    I didn't see any issue with schematic except the note regarding series resistors (22 Ohm to 100 Ohm) but resistors are not in the schematics.

    This is a very simple device and mmost probably you have a simple error. For debug verify the following tests/checks:

    1-Verify all supply voltages are correct  at THE PIN of the IC

    2-Vneg is very critical, make sure you have -3.3V at VNEG pin. If any issue with VREG, check the related caps to charge pump pins  (and their  polarity-- if applicable) 

    3- The format(=LOW)  is set for I2S, verify that what you are  sending to the DAC is  indeed I2S---- if it is RJ , LJ and etc, DAC will not workas it is expecting I2S

    4- XMST is pulled high correctly, so it is not muted, nevertheless verify it at the pin

    5- Table 10. shows the correct System Master Clock for a given Fs,  use the exact clk per table.

    If all of the above are verified and still you have  no output, Reopen this post and include the  screen captures for all the I2S signals so we can review the relative position of the edges with respect to each other.

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    Intellectual 420 points

    Hi Arash，

    When we no longer supply SCK to PCM5102A,OUTL can output the signal.

    Could you help to explain why?When is SCK needed?

    Thanks.

  • 0 in reply to Rubin Chen
    TI__Mastermind 30781 points

    Few things to watch. First, the SCK has to be within the spec mentioned in datasheet and second  the synchronization of LRCK and system clock. If the relationship between LRCK and system clock changes more than ±5 SCK, internal operation (using an on chip oscillator) is initialized within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and system clock is completed and as long as the   synchronization of LRCK and system clock is not achieved, there will be no output.   However if you remove SCK, the device starts up expecting an external SCK input, but if BCK and LRCK start correctly while SCK remains at ground level for 16 successive LRCK periods, then the internal PLL starts, automatically generating an internal SCK from the BCK reference.

    From the above, it seems you have a problem with synchronization of LRCK and system clock and once you remove it, the PLL takes over and generates it internally and everything works fine. So your best choice is to  use 3wire option (no external SCK)  you verified on bench it is working with 3 wire option.

    Regards,

    Arash