Tool/software:
Hello TI.
The DIT4192 datasheet recommends to put 0.1 uF capacitor next to the TX- pin for AES3 layout.
In the mentioned topic (discussing SPDIF) you choose to put 1 uF capacitor next to TX+ pin. Does value and location matter for AES3 and SPDIF? Or can I use same values and location for both of these interfaces?
* A print screen from the mentioned topic:
