TAS6424-Q1: "Clock fault detected" fault occurs & mclk waveform offset occurs. Are these two things related?

Hi

?? ? said:

Our project is using tas6424-q1.
Our problem is that the waveform of mclk is not normal. There is an offset.
How can we fix this problem?

I'm afraid this is not TAS6424 related. 

Please check on your board, where is MCLK signal coming from. If it is from SOC GPIO pins, check what is the original signal without the load. Also check if there's any additional pull up/down on your board.

?? ? said:

Can mclk cause a "Clock fault detected" fault? We are currently experiencing a "Clock fault detected" fault interrupt.

Yes, MCLK will results in Clock Fault.

Dear  shadow he

We use LSF0108 level shifter between AP and TAS6424.

If we remove R1637/R1644, the waveform becomes very clean.
However, it does not step up from 1.8V to 3.3V.
Because of the level shifter, there is a problem with the mclk waveform, which causes clock fault.
Could you please tell me about this part?

LSF0108 level shifter is also a TI product. Please let me know if this level shifter is suitable for sending a clock of 6MHz or higher.

Hi

 Please have a try, to follow the Up-Translation in the datasheet. Only keep the 3.3V side pull up resistor, and remove the 1.8V side pull up.

?? ? said:

Please let me know if this level shifter is suitable for sending a clock of 6MHz or higher.

Should be no problem.

Dear Shadow He

thanks a lot,
I removed the 1.8v pull-up resistor and the offset voltage disappeared
The max voltage on the 3.3v side is measured as 2.5v. I want to give this part a stable margin of 2.9v or more and solve the problem of the waveform becoming sharp. It's still a clock fault.

I have one more request.
The clock shape is sharp. How can I make it flat?

When I remove all the pull-up resistors, the clock shape is square if it passes through the level shitter. When I connect the pull-up resistors, the clock shape becomes sharp. However, if there is no pull-up resistor, the output is 1.8 as it is on the b-side. I am in a very difficult situation.

Dear Shadow He

I tried this circuit diagram.
The max voltage went up to 2.9v, but there is no flat part in the clock.
What could be the problem?

Hi

The results still looks quite bad. Could you also capture the waveform at 1.8V side? Is there a quite clean clock waveform?

And let transfer this Thread to TXP team, they should be more familiar with this device. 

Dear shadow He

Thank you so much for your sincere answer.

I will send you the mclk signal that is input to a side.

I will also ask the txp team for help.

https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1520393/lsf0108-q1-i-m-having-trouble-connecting-i2s-to-lsf0108?tisearch=e2e-sitesearch&keymatch=lsf0108%20i2s#

I have registered an issue in the logic part.

Where is the txp team?

Dear shadow He

My company's hw team says the clock fault is a software issue.

He told me to increase the time and send it again when I sent the waveform to TI for confirmation.

Is the attached waveform normal? The fault still occurs. I want to check if it is a software issue or a hw issue. Please help.

Input wave (A- side)

Output wave (B-side)