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Original question:

TAS3251: I2S Master-Mode

TAS3251: I2S Master mode

Sia Rezaei
Prodigy 120 points

Part Number: TAS3251

I have developed a board based on TAS3251. I'm trying to configure it to be I2S master (i.e. drive SCLK and LRCLK). The following is my configuration. I have only added the section between "I2S master begin"  and "I2S master end". The rest is what PPC3 generated. However, the device does not generate SCLK or LRCLK. What am I missing? 

{"addr":"0x00","value":"0x00", "comment":"program memory"}
{"addr":"0x7F","value":"0x00"}
{"addr":"0x02","value":"0x11", "comment":"standby request + power down request"}
{"addr":"0x01","value":"0x11", "comment":"reset module and reset register"}
{"addr":"0x00","value":"0x00"}
{"addr":"0x00","value":"0x00"}
{"addr":"0x00","value":"0x00"}
{"addr":"0x00","value":"0x00"}
{"addr":"0x03","value":"0x11", "comment":"Mute left and right channels"}
{"addr":"0x2A","value":"0x00", "comment": "Zero data DAC data paths i.e. mute"}
{"addr":"0x25","value":"0x18", "comment": "Ignore MCLK Detection + Ignore Clock Halt Detection"}
// I2S master begin
{"addr":"0x09","value":"0x11", "comment": "Turn SCLK and LRCLK to output"}
{"addr":"0x0C","value":"0x00", "comment": "Reset SCLK and LRCLK dividers"}
{"addr":"0x20","value":"0x07", "comment": "MCLK divider to get SCLK"}
{"addr":"0x20","value":"0x40", "comment": "SCLK divider to get LRCLK"}
{"addr":"0x0C","value":"0x03", "comment": "Enable SCLK and LRCLK dividers"} // needed?
{"addr":" 0x1C","value":"0x1F", "comment": "DAC clock divider for 48kHz"}
// I2S master end
{"addr":"0x0D","value":"0x10", "comment": "The PLL reference clock is SCLK - ignored in auto clock mode"}
{"addr":"0x02","value":"0x00", "comment": "Enable the device"}
{"addr":"0x00","value":"0x00", "comment":"Enable sub channel / YM host buffer"}
{"addr":"0x7F","value":"0x8C"}
{"addr":"0x00","value":"0x1D", "comment":"prm_nosub"}
{"addr":"0x28","value":"0x00"}
{"addr":"0x29","value":"0x00"}
{"addr":"0x2A","value":"0x00"}
{"addr":"0x2B","value":"0x00"}
{"addr":"0x00","value":"0x00", "comment":"Sample rate update"}
{"addr":"0x7F","value":"0x00"}
{"addr":"0x02","value":"0x80", "comment": "Reset DSP"}
{"addr":"0x00","value":"0x00"}
{"addr":"0x7F","value":"0x00"}
{"addr":"0x22","value":"0x03", "comment":"speed 03-48k 04-96k"}
{"addr":"0x00","value":"0x00"}
{"addr":"0x7F","value":"0x00"}
{"addr":"0x02","value":"0x00", "comment": "Enable the device"}
...

Thanks,
  • 0
    Prodigy 120 points

    Two more things to add:

    1. I fixed the address for "SCLK divider" i.e. 0x20 -> 0x21. That doesn't solve the issue

    2. If I remove the section between "I2S master begin"  and "I2S master end", this config works fine with the device in slave mode.

  • 0 in reply to Sia Rezaei
    TI__Guru** 114555 points

    Hi Sia,

    What is the MCLK frequency you use?
    Note the information provided in data sheet from page 23 through page 30. The proper input clock must be selected, then the clock dividers and PLL if needed.

    Best regards,
    -Ivan Salazar
    Applications Engineer