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PCM1865: Design Support for PCM1865, PCM5122

Al Walker
Prodigy 10 points

Part Number: PCM1865
Other Parts Discussed in Thread: PCM5122,

I am working on an audio converter reference design to be used across multiple projects. I have a high quality clock source providing MCLK, BCLK and LRCLK/FSYNC and therefore want to use both the PCM1865 and PCM5122 in I2S/TDM peripheral (slave) mode. 

Could you confirm if the modes of operation as shown in the block diagram can be supported, and if possible the required register settings please?

I also note that BCLK needs to be stopped when changing sample rate. I can do this by gating the LMK1C1104PW with the BCLK_ENABLE signal. Are the MCLK and LRCLK/FSYNC clocks also required to be stopped when changing sample rate please?

 

260222 Audio Converter Development Board.pdf 

  • 0
    TI__Mastermind 21486 points

    Hi Al,

    I think all the configurations look fine. Here are the important things to check:

    I2S:

    • Only 2 channels per digital data line
    • BCLK = 64*Fsync

    TDM:

    • BCLK = 256*Fsync
    • Make sure TX_OFFSET is set properly on each PCM1865 (Register 13) and RX_OFFSET is set properly on each PCM5122 (Register 41).

    Also make sure MCLK is maximum 50MHz. From what you shared, it appears all these criteria are met, as long as the offsets are configured appropriately.

    I would stop all clocks when changing the sample rate.

    Best,

    Garret

  • 0 in reply to Garret Godfrey
    Prodigy 10 points

    Hi Garrat,

    Thanks very much for the clear and concise answer. 

    Kind regards,

    Al