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AIC3254 AEC implement for Samsung Refrigerator

Dear team,

 

I am making a script of AIC3254 AEC(Echo cancellation) with 8kHz sampling rate for Samsung smart home project needs AEC for refrigerator...

and get the attached codec/mDSP script and get the right operation...

 

However, Samsung is asking the bypass of AEC and non audio processing with 48kHz sampling rate under smallest modified setting from AEC script..

Actually, I got this below setting to have the bypass mode but we need full AEC script with RESET again whenever we switch AEC and non AEC each other..

it take more than 1sec time with 400kHz I2C speed to write each initialization about AEC(8kHz PLL and mDSP processing) and non AEC(48kHz and mDSP bypass) whenever mode change..

Samsung is asking <100mS to chage the mode!!!!

Please help me to find out the way to swith the two mode with minimum script..

- 48kHz normal processing (only codec setting + PRB1 processing )

- 8kHz AEC processing ( Codec setting + PLL + mDSP processing on)

 

Thanks and best regards,

JY- Samsung account.

 

 ------------------- 48kHz non audio processing ----------------------------------------------------------------------------

# High Performance Stereo Playback

# ---------------------------------------------

# PowerTune mode PTM_P3 is used for high

# performance 16-bit audio.

#                                                  

# Audio is routed to both headphone and

# line outputs.

###############################################

 

 

 

###############################################

# Software Reset

###############################################

#

# Select Page 0

w 30 00 00

#

# Initialize the device through software reset

w 30 01 01

#

###############################################

 

 

 

###############################################

# Clock Settings

# The codec receives: MCLK = 12.288 MHz,

# BLCK = 3 MHz, WCLK = 48 kHz

###############################################

#

# Select Page 0

w 30 00 00

#

# NDAC = 1, MDAC = 2

w 30 0b 81 82

#

###############################################

 

 

 

###############################################

# Signal Processing Settings

###############################################

#

# Select Page 0

w 30 00 00

#

# Set the DAC Mode to PRB_P1

w 30 3c 01

#

###############################################

 

 

 

 

###############################################

# Configure Power Supplies

###############################################

#

# Select Page 1

w 30 00 01

#

# Power up AVDD LDO

w 30 02 A9

#

# Disable weak AVDD in presence of external

# AVDD supply

w 30 01 08

#

# Enable Master Analog Power Control

# Power up AVDD LDO

w 30 02 A1

#

# Set the input power-up time to 3.1ms (for ADC)

w 30 47 32

#

# Set the REF charging time to 40ms

w 30 7b 01

#

###############################################

 

 

###############################################

# Playback Setup

###############################################

#

# Select Page 1

w 30 00 01

#

# De-pop: 16 time constants, 6k resistance

w 30 14 35

#

# Route LDAC/RDAC to HPL/HPR

w 30 0c 08 08

#

# Power up HPL/HPR and LOL/LOR drivers

w 30 09 3C

#

# Unmute HPL/HPR driver, 0dB Gain

w 30 10 00 00

#

# Select Page 0

w 30 00 00

#

# DAC => 0dB

w 30 41 00 00

#

# Power up LDAC/RDAC

w 30 3f d6

#

# Unmute LDAC/RDAC

w 30 40 00

#

###############################################

 

###############################################

# High Performance Stereo Recording

# ---------------------------------------------

# PowerTune mode PTM_R4 is used for high

# performance 16-bit audio.

#

# IN2L/R is routed to the LADC/RADC in a

# single-ended manner.

###############################################

 

 

###############################################

# Clock Settings

# ---------------------------------------------

# The codec receives: MCLK = 12.288 MHz,

# BLCK = 3 MHz, WCLK = 48 kHz

###############################################

#

# Select Page 0

w 30 00 00

#

# NADC = 1, MADC = 2

w 30 12 81 82

#

###############################################

 

 

 

###############################################

# Signal Processing Settings

###############################################

#

# Select Page 0

w 30 00 00

#

# Set the ADC Mode to PRB_P1

w 30 3d 01

#

###############################################

 

 

 

###############################################

# Recording Setup

###############################################

#

# Select Page 1

w 30 00 01

# Mic Bias on

w 30 33 60

# Route IN3L to LEFT_P with 20K input impedance

w 30 34 08

#

# Route CM1L to LEFT_M with 20K input impedance

w 30 36 80

#

# Route IN3R to RIGHT_P with 20K input impedance

w 30 37 08

#

# Route CM1R to RIGHT_M with 20K input impedance

w 30 39 80

#

# Unmute Left MICPGA, Gain selection of 20dB to make channel gain 0dB

# Register of 6dB with input impedance of 20K => Channel Gain of 0dB

w 30 3b 26

#

# Unmute Right MICPGA, Gain selection of 20dB to make channel gain 0dB

# Register of 6dB with input impedance of 20K => Channel Gain of 0dB

w 30 3c 26

#

# Select Page 0

w 30 00 00

#

# Power up LADC/RADC

w 30 51 c0

#

# Unmute LADC/RADC

w 30 52 00

#

###############################################

 

 

 

 

AIC3254 initial setting with 8kHz AEC on.docx
  • Hi Ji-Yong,

    Of course, the best solution is to ask customer to use 5MHz or so SPI, which increases download speed > 10x.

    For AEC process flow, it seems that the download time might not be optimized. Based on the script you provided the download time would be close to 150ms, not 1 second. I suggest you to verify the I2C transactions on a scope to observe the timing. Also, make sure C-RAM and I-RAM bytes are sent as 120 auto-incremented bytes per page (30 coefficients / instructions per page). For each C-RAM/I-RAM page write, there are 120 bytes of data + 2 + 3 bytes of overhead to set page.

    The I-RAM memory is retained even after a software or hardware reset. So one trick is to write the I-RAM section once at boot-up (or whenever power is removed) and then skip I-RAM writes for mode changes (write everything except I-RAM). This should save around 65% of download time when switching modes conpared to downloading I-RAM. With my calculations, this should take 44ms.

    Summary:

    • Fix i2c communication / i2c script parsing such that the result is close to 150 ms.
    • Do the I-RAM trick to reduce download time close to 50ms.
    • If the above is not possible, use SPI.

    Let me know if you need clarification.

    Regards,

    Jorge

  • Hello Arbona,

     

    Thanks for your support!

    Samsung replied they could modify the circuit from I2C to SPI for faster download of script.. BTW,

    they need Linux driver to set each attached script for AEC(8kHz) and non AEC(48kHz).. due to system SOC environment.. 

    How can I get the linux driver of AIC3254..?

     

    the problem is,

    Attached my linux driver file from your team doesn't have header file for audio.etc...

     

    Thanks and best regards,
    JY - Samsung Account.

     

     

  • Hi JY,

    Do you know you can generate header files with PPS? See this wiki page: http://e2e.ti.com/support/data_converters/audio_converters/w/design_notes/2823.how-to-generate-a-header-h-file-with-pps.aspx

    Have you seen this post about linux drivers? http://e2e.ti.com/support/data_converters/audio_converters/f/64/t/266169.aspx

    Let me know if this helps you support this oppy if you need anything else.

    Thanks,

    Jorge