My question arises from trying to understand how the output bitstream of a Sigma Delta converter is generated from a given input code.
A colleague pointed me at slyt076 to try and help me understand, but we both ran in to some confusion over the example given for the 3-bit DAC with a 011 input code provided in Table 1.
Table 2 on the same page makes logical sense to me in terms of how the zero stuffing works and where would be the ideal locations to stuff the zeros for each code. Essentially the added zeros end up equally spaced, with more zeros present for lower input values. Great, that makes perfect sense. The bitstream for a 011 input in Table 2 also conveniently matches the graphical representation for an input of 011 from Figure 2, that is 01001010. Again, great, that makes sense and matches, and 3 out of 8 high pulses passed through a low pass filter averages out to 3/8 of full scale, awesome.
This brings me back to Table 1, which attempts to show the step by step iteration for each bit of the bitstream output as it is derived from the 011 input. The only problem is, that even after you throw away the first DAC output value (bit 0) from the initialization iteration, bits 1 through 8 of the DAC output in Table 1 do not match bits 1 through 8 of the DAC output in Table 2 for a 011 input.
Is this a mistake in Table 1? If it's not a mistake, what am I failing to understand? If it is a mistake, how should Table 1 look if corrected?
I tried doing the table myself by following the algorithm given in the Figure 3 flow diagram, but I get very incorrect results so I assume I'm going something very wrong. To be honest, I'm not even completely sure what that diagram means by the "Sigma[N+1:0]" feedback term, but when I look at Table 1, every iteration after the initialization has Sigma equal to the value of Sigma_Out from the previous iteration.
Can anybody understand that mess I just blurted out above and help me out?
