This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi Community,
I have been tinkering with the TAS5756 and trying to establish the behavior of the clock auto set mode P0-R37 bit 1. The earlier datasheet describes in sparse detail those settings that are ignored when auto set is activated but does not describe much about the behavior of auto set mode itself.
My specific question is whether auto set clock mode can operate in the absence of an externally applied MCLK such that the PLL will be programmed and take is source from either BCLK or SCLK. Right now it appears not to work without an externally applied MCLK and that it is necessary to program the PLL manually which is a pity because it will require reprogramming of the PLL for any change in the sampling rate of the source.
Hi Killian,
The auto set works. It's used to set up the PLL and internal clocks divider ratios.The device doesn't know that MCLK is intentionally missing, so you will have to set the PLL source clock to SCLK/BCLK (MCLK is defalut) and tell the device to ignore MCLK errors. If you don't want to do any programming, you can connect SCLK signal with MCLK (once the SCLK is with MCLK frequency range > 1MHz).
Thanks Damian,
I tried your suggestion on PLL source select and set the 'ignore clock error' flags and it worked great for 44.1 and 48KHz at all bit depths.
I tried 96KHz and 176.4KHz audio but the minidsp appears to mute the output if set to "User Program in RAM". Most other DSP preset settings seem to be fine when setting P0=0x2B to 0x01, 0x02 or 0x03.
I then realized that Hybridflow 1 only supports up to 48KHz and that for higher sampling rates, Hybridflow 5 or 7 must be used.
Its a great device!
Hi Killian,
Thanks for the awesome validation of TAS5756M. We're happy to kow that TAS5756M meets your requirements and helps solve your challenges!
Thanks again for the feedback!!