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TLV320DAC3100: I2C Fast mode?

David F. Chan
Expert 5440 points
Part Number: TLV320DAC3100

Hi all,

To clarify on the DAC3100's I2C Fast mode, can you please share what the max pull-up resistance vs. bus capacitance is when operating in standard vs. fast mode?

Also, is this handled automatically (say, if the I2C master on the bus runs SCL at 120kHz? How does the device know when to run fast mode (this would be a different matter, as the master on the bus would then violate the SCL/SDA rise and fall times).

  • 0
    TI__Guru* 84915 points
    Hi, David,

    I recommend to take a look at the following document. It contains information about the I2C parameters. Additionally, it contains a max pull-up resistance vs. bus capacitance graph:

    www.ti.com/.../slva689.pdf

    The device automatically recognizes if the I2C lines are being used in standard or fast mode.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    TI__Expert 5440 points
    Hi Luis,

    Got it, thanks! So basically we only spec both for legacy reasons. Is there a particular reason why there is a lower limit at all for the rise/fall times (does too quick translate to too strong a pull-up resistor to meet the Fast mode spec?)
  • 0 in reply to David F. Chan
    TI__Guru* 84915 points
    Hi, David,

    The specified lower limit is due to the capability of the I2C interface to recognize the falling/rising edge. Depending of the capacitance at the I2C lines, the I2C interface would require of more time to detect the falling/rising edge.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    Genius 5095 points

    Dear David,

    Are there any concern if the I2C rise/fall time is lower than the specified lower limit of TLV320DAC3100?

    Below are the measure waveform. Rise=2.5ns, Fall=3.8ns.

    Please help to confirm.

    Thanks

  • 0 in reply to daniel
    TI__Guru* 84915 points
    Hi, Daniel,

    We cannot guarantee that it will work correctly since the I2C rise/fall time is lower than the specified lower limit. However, this shouldn't be a problem if the I2C interface is configured in standard mode.

    Best regards,
    Luis Fernando Rodríguez S.