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TLV320AIC23B: ADC-DAC issues with MCLK=BCLK and core clock MCLK/2 (CLKIN = 1)

Carlos Ilarregui
Prodigy 50 points
Part Number: TLV320AIC23B

My application uses the TLV320AIC23B as slave with 12.288 MHz external clock in DSP mode.  

The same clock is used for MCLK and BCLK and the external synchronous generation generation of LRCIN and LRCOUT

No problems observed at 8 KSPS (SR = 00110) or 32 KSPS (01100) when using MCLK = BCLK and CLKIN = 0 (no MCLK divider).

But I need a sampling rate of 16 KSPS.  Since the part does not directly support 16 KSPS, I selected the 32 KSPS (01100) sampling rate and reduced the core clock to MCLK/2 (CLKIN = 1 @ Reg8 b6)

Limited tests show a substantial distortion (harmonic?) at both DAC outputs.

I did not find any restrictions on the ratio of the two clocks.  I know that the frame rate should be synchronous with MCLK (satisfied) and BCLK in required to be sufficient to transfer the number of data bits required in each sample interval (also satisfied).  I did not find any restrictions on the ratio of the two clocks.

I'll appreciate any ideas or suggestions.

  • 0
    TI__Guru* 84915 points
    Hi, Carlos,

    Welcome to E2E and thank you for your interest in our products!

    I will take a look at this and will answer as soon as possible.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    TI__Guru* 84915 points
    Hi, Carlos,

    Could you tell me which MCLK frequency are you using?

    I searched for some information about this. If you use MCLK at 1/2 of the listed number, the sample rate will be 16 kHz. So for instance if you choose the MCLK of 12 MHz in the first table (32 kHz = SR3=0, SR2=1, SR1=1, SR0=0, BOSR=0) and set MCLK to 6 MHz, the sample rate will be 16 kHz. You could also set it for 8 kHz and double MCLK but you would have to stay bellow max MCLK of 19 MHz so 32 kHz and MCLK*0.5 is the best option.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0
    Prodigy 50 points
    
    Luis,
     
    My system has two fixed requirements:  BCLK @ 12.288 MHz and 16 KSPS Sampling Rate.
     
    I'm using MCLK = BCLK = 12.288 MHz and dividing MCLK by 2, so the internal core clock is MCLK/2 = 6.144 MHz.
     
    I'm also setting the sampling rate bits for 32 KSPS @ 12.288 MHz, that should result in 16 KSPS when using MCLK = 6.144 MHz
     
    The problem is that I get all sort of audio artifacts when I do that.
     
    Are there any requirements like BCLK not to exceed the internal core clock (MCLK/2)?
     
    The only items that I found in the data sheet indicate that:
     
    1.  BCLK is ONLY used to shift data in and out.
     
    2.  MCLK should be synchronous with the Frame Rate (my application satisfy this).
     
    Best regards,
     
    Carlos Ilarregui
    CIE Engineering Inc
    carlos@cie-eng.com
    office:   (305) 907-1883
    mobile: (703) 922-7061
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