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TLV320AIC3204: TLV320AIC3204 capture problem

Part Number: TLV320AIC3204

Hi,

We are planning to use TI codec TLV320AIC3204 with our Qualcomm 820 based custom board, but due to some problem capture is not working with current configuration. Data captured are either all zero(when MCLK is applied) or some garbage(When Mclk is not applied) and not able to play.

We are using TLV320AIC3204 EVM for initial verification

We are using TI coded in slave mode with following clock applied on capture.

MCLK - 24 MHz (Generated externally)

BCLK - 1.53 MHz (Generated by 820 board)

WCLK - 48 KHz (Generated by 820 board)

We are capturing using onboard MIC(IN3 line) and all W1 to W8 jumpers are set to their default position.

Following is our I2C register configuration for capture.

Page 0

0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 00 00 50 00 00 11 04 00 00 00 00 01 01 00 80 02 ..P..??....??.??
10: 00 08 01 01 80 01 00 04 00 00 01 00 00 00 01 31 .?????.?..?...?1
20: 02 0c 00 00 44 00 00 00 00 00 00 00 00 00 00 00 ??..D...........
30: 00 00 00 00 04 02 03 02 02 00 00 00 01 01 00 14 ....?????...??.?
40: 0c 00 00 00 6f 38 00 00 00 00 00 ee 10 d8 7e e3 ?...o8.....???~?
50: 00 00 00 10 10 00 80 00 0a 00 00 00 00 00 00 00 ...??.?.?.......
60: 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ?...............
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

Page 1

0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 01 08 01 00 00 00 00 00 00 00 00 10 00 00 00 00 ???........?....
10: 40 40 40 40 00 00 00 00 00 00 00 00 00 00 00 00 @@@@............
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
30: 00 00 00 40 04 00 04 00 00 00 00 46 46 00 00 00 ...@?.?....FF...
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

We are facing following two problems.

1. When 24MHz MCLK is applied

On capturing audio using "tinycap" utility, dumped file contain data as all zero. I2C command return all register as XX after capture started and remains as it is until next reboot.

2. When 24MHz MCLK is removed

Capture show some data in file, but trying to play that file using "tinyplay" utility show error message "Error: '/data/rec.wav' is not a riff/wave file".

In both above case if I check DIN/DOUT test pin there is no significant voltage change when capture is started. Voltage remains around 400-800 mV.

Thanks,

Pratik

  • Hi, Pratik,

    There are a couple things that could be causing the issue, perhaps related more to the controller than the codec. Is the data captured saved in an audio format which can be read by the processor?, the AIC3204 outputs PCM data that should be interpreted by the processor to read it as a sound file.

    Is it possible to share a different type of register settings which can explain what is the intended configuration of the device?. From your configuration I'm seeing that MCLK is the input for the internal clocks, which tells me that the device is not being operated properly as there is no clock source driving the internal clocks.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer