TLV320ADC3101: TLV320ADC3101

hi,

1. Due to the need for additional audio input, the TLV320ADC3101 is used, and then the circuit is gradually debugged. First, the I2C bus uses the oscilloscope to observe the waveform, and the corresponding waveform is normal. Then the DMCLK/GPIO1 pin is configured as GPIO to output the logic level 0 or 1, when the GPIO 1 pin waveform normal, if set to other, abnormal output, no clock waveform.

2.

AUDIO_RESET: connection reset signal;

  AUDIO_MCLK: 12Mhz signal;

3, register configuration:
Procedure description:
Where the serial number indicates the initialization sequence;
Lut_data <={8'hAA,8'hBB}; indicates that 0xBB is written to the 0xAA register.
AA, BB are all hexadecimal data
For example: 6: lut_data <= {8'h08, 8'h80}; // indicates that after the reset step 6, write 0x80 to the 08 register;

Specific initialization:
No. Register Initialization Remarks
0: lut_data <= {8'h00,8'h00}; //Set page0
1: lut_data <= {8'h01,8'h01}; //sw rst
2: lut_data <= {8'h04, 8'h03}; // Set the clock: PLL_CLKIN=MCLK, CODEC_CLKIN=PLL_CLK;
3: lut_data <= {8'h05, 8'h91}; // Set the PLL parameters: P=1, R=1, and enable the PLL
4: lut_data <= {8'h06,8'h0C}; //J=12 // J.d=8.1920
5: lut_data <= {8'h07,8'h07}; //d:MSB
6: lut_data <= {8'h08,8'h80}; //d:LSB
7: lut_data <= {8'h12,8'h88}; //NADC=8
8: lut_data <= {8'h13,8'h82}; //MADC=2
9: lut_data <= {8'h14,8'h80}; //AOSR =128 (default)
//(2) program I2S word length
10: lut_data <= {8'h1B, 8'h0C}; //AUDIO INTERFACE, (I2S, wordlen=16bit, BCLk(output), wCLk(output))
11: lut_data <= {8'h3d, 8'h01}; // ADC Signal Processing Block: PRB_R1
12: lut_data <= {8'h34,8'h10}; // DMDIN/GPIO1= CLKOUT output
//3, porgam AD blocks
13: lut_data <= {8'h00, 8'h01} ;//settings page 1
14: lut_data <= {8'h33, 8'h78}; //program micbias 3.3V
15: lut_data <= {8'h3b,8'h00}; //program left analog PGA (default)0db
16: lut_data <= {8'h3c,8'h00}; //program right analog PGA (default)0db
17: lut_data <= {8'h34,8'h3F}; //left adc pin select (IN2L(P), IN3L(M))
18: lut_data <= {8'h37,8'h3F}; //right adc pin select (IN2R(P), IN3R(M))
//4,program ADC;
19: lut_data <= {8'h00,8'h00}; //set page 0
20: lut_data <= {8'h51,8'hC2}; //power up left adc and right adc;
21: lut_data <= {8'h52,8'h00}; //dis mute ;
22: lut_data <= {8'h19,8'h00}; // CLKOUT MUX:CDIV_CLKIN = MCLK
23: lut_data <= {8'h1A,8'h81}; // CLKOUT divider M = 1, CLKOUT M divider is powered up.
24: lut_data <= {8'h35, 8'h14}; // DOUT Pin=0 (Audio_dout pin setting)
25: lut_data <= {8'h35,8'h15}; // DOUT Pin=1
26: lut_data <= {8'h35,8'h14}; // DOUT Pin=0
27: lut_data <= {8'h35, 8'h16}; // DOUT Pin = CLKOUT output ;

Tested oscilloscope observation
Audio_dout and GPIO1, GPIO2 pin set to 1 or 0, are normal;
When set to clkout, no clock waveform output;