TPA3255: Dual TPA3255 used in parallel with PBTL Mode

Adam, 

I apologise if I was not clear. I have not connected a TPA3255 with an ST product. What I referenced was connecting in parallel 2 ST class D amps. In fact they had this defined as a working option within an application note. However in TI's defense I finally switched to the TPA3255 for other reasons, one of which was superior protection systems.

Anyway I digress, my question still stands....this would indeed be a very useful configuration. In my own application it is not so much about increasing output power but rather managing thermal stress.  The TPA3255 is a very very small device and if you run it hard for any length of time, removing heat from the substrate is challenging, any configuration that could make this better is indeed useful. Now clearly 2 chips in parallel has the potential to keep things a lot cooler, but obviously at a cost. 

Again finally, with this configuration I am suggesting that by creeping the supply voltage up you might also increase total output power without exceeding any OC protection and still maintain the IC within heat stress limits.

If we look at the maths we can see a small Vdd increase results in dramatic power increases. Taking a look at the speaker current, in class D we see:

Ispk_peak = (2*Vdd/Rl)*(D-0.5)

For the TPA3255 we can assume a modulation index (D) of ~ 0.97

Therefore at Vdd = 53.5V and Rl = 3ohm, we have Ispk_peak = 16.763 amps

Pout_rms = (Ispk_peak^2*Rl)*.707

Pout_rms = 596.02W.

This is as defined by the spec sheets.

Now if we as an example take the Vdd up to 59V which is still below the absolute maximum (69V), but well above recommendations. What is not defined is the Boot strap level above Vdd. However I assume this will be only 8-10V above Vdd, maybe less? I have not actually measured it. But this is typical and if correct this would still maintain the IC below absolute maximum values. (just)

Doing the maths for this case:

Ispk = 18.486 and Pout_rms = 724.8W. An output power increase of 21.6% for just 5.5V extra Vdd. As we can see the current is very high and above the maximum OC for the IC. If however we can split this between 2 ICs then it falls to well within the limits and might actually prevent the ICs from tripping OC (as mentioned in the original thread) and with the added bonus of a huge reduction in thermal stress.

I am using the TPA3255 within an pro audio PA system I am designing, therefore expect very heavy use, one might even say abuse!

Perhaps you can consider this use case I have described and comment on the voltage levels and current sharing?

Aidan

Aidan,

How do you plan on syncing the output of the two ICs?

Regards,

-Adam


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Hi Adam,

Hey, I didn't say this was possible, but if you look at the thread before me Juston Bohr, who is a TI employee stated that they have experimented with this configuration. So this gave me some hope that it might be possible. Looking at the chip we have OSC_IOM and OSC_IOP. With very limited info about how to use them, but I guess that setting one IC as master and having the other clocked from it might offer a solution that ensures at least the MOSFETs are switched synchronously. However having said this all the feedback loop on the TPA3255 is internal and nothing exposed, so it certainly would not surprise me that regardless of synchronisation, having two independent  closed loop systems is I would think rather likely to be unstable. 

As I said it would be wonderful if this is possible, but I'm not the expert, I'm just struggling with the reality of squeezing a lot of power out of the IC reliably. The TPA3255 is an impressive sliver of silicon, thanks for that, but it sure as hell gets hot!

Please understand that I am only exploring any route that might give a little more for a little less. When I look at the specs for the TAS5634, which on the surface simply seems to be a PWM input version of the TPA3255, I can see that it is rated at 58V Vdd. It is described as a thermally enhanced package, but what that actually means I do not know. Physically it seems to look identical to the TPA3255 and even the RDSon of the output MOSFETs are identical. So you might forgive me for asking if it is not indeed possible to push the TPA3255 up to the same supply voltage. Having said this, I already had a similar discussion with other TI folks, I recognise the need to handle the potential currents and I have already gained hard won experience of what happens if this is not controlled. Its pyrotechnic!

So to avoid setting fire to any more amplifier ICs I'm hoping to explore other options to spread the load.

All the best

Aidan 

Adam, as a side issue it might be worth asking this question again. OC protection is stated as being measured individually on all low and high side FETs. Now IMHO it is not clearly stated that this current measurement is adjusted when operating in PBTL. The datasheet simply mention the 4 possible levels, but if we operate in PBTL is it still fair to assume that the OC trip point will not be actually valid with respect to the load. That is because the current will split between the parallel output FETs on both low and high side and therefore given that the max OC level is 17A then either this value is adjusted to still be 17A ( i.e the sum of both FET currents when in PBTL) or its still 17A per MOSFET, in which case how can the OC protection be tripped as we would then have a max current of 34A total before any OC sense is triggered. Simply knowing what is actually happening in case of BTL, and PBTL in term of OC protection would be helpful. It is not in my opinion clear from any datasheet provided.

But perhaps, I cant read so well and I am to assume that this change of totalling up the currents is an intrinsic feature of operating in PBTL mode. Do please clarify if possible.
Aidan

Aidan,

Section "10.2.1.2.4 Oscillator" in the datasheet talks about the OSC pins and using them for slave operation of multiple devices. This is designed such that multiple devices can be cascaded and distribute out the board heat and power supply loading by timing the outputs of all board devices staggered. 

This app note discusses it more: http://www.ti.com/lit/an/slaa787/slaa787.pdf

Justin actually tried this approach recently to try and reach double the power of one device and was not successful. We tried to sync multiple devices with shared outputs by driving both devices with the same external clock on the OSC pins. 

That being said, if you're trying to output only half the power of one device per device, this may work. Put both devices in Slave mode and feed both devices with an external differential clock in the SAME polarity. Check to make sure the associated outputs are synced with a scope before pushing big power to a speaker.

Regards,

-Adam

Thanks Adam, 

That's interesting and thanks indeed for the app note. Very clear, now I understand the primary use case well. 

I may, given some time and a fair wind, try to emulate the setup. Do you have any further details of the specific configuration including that of the external oscillator. 

However, equally important are all the other questions I asked about OC detection and the specific details of this is PBTL mode, as well as the questions regarding Vdd higher than 53.5V. After all it was under higher voltages that I found destructive events occuring. What is unclear is did this happen due to voltage stress, overcurrent stress or thermal stress. Without knowing these more intimate details I'm stabbing in the dark.

I would like to raise Vdd to 58V if possible. Its certainly the simplest way to increase power levels. Even if multiple devices are paralleled the Vdd level still the primary factor in determining the upper limit on output power. My ideal scenario would be to increase Vdd and simultaneously parallel multiple amplifiers to spread the extra load. Because as I explained, thermal issues definitely become a problem at high power levels with this IC. 

Thanks again and please allow me to make it clear, I am not asking anything to be underwritten or accepted as legitimate use by TI. I'm simply hoping that you guys can help me to push the limits with as much information as you are happy to share.

All the best

Aidan

Hi Adam,

I know my questions must be frustrating, but please could you clarify. I have been taking a look at the output pins on the TPA3255 directly when under heavy load. I am running the device at 50.5V Vdd, When I measure the voltage directly at OUTX to GND I see transients at the switch transitions that reach somewhat above the supply rail and likewise below GND in the opposite direction. These measure at 53.34V on the positive going edge and -2.73V on the negative going edge. The datasheet for the TPA3255 does not seem to mention any transient timings for voltage levels on the OUTX pins. However the datasheet for the TAS5634 does. It states -7V or +71V for no more then 8nS. This info as I said is not shown for the TPA3255. If I wish to try raising Vdd once more then I would like to pay very careful attention to these transients. Could you please help me and try and obtain similar data for the TPA3255. Hopefully so long as these transients remain relatively constant then I can aim to keep the design with SOA. But I need the details of this for the TPA3255.

Thanks

Aidan

Aidan,

The external signal should be similar to the signal coming out of the OSC pins when in master mode except provided externally and both devices are to be in Slave mode. 

Do not exceed the recommended MAX voltages, this silicon is not the same as the TAS5634, it's very different.

Regards,

-Adam

Aidan,

This data is not something we have measured. The difference between recommended max and absolute max is to account for transients like this and additional safety headroom so that the devices don't get damaged. I cannot recommend that you raise the PVDD any higher than the recommended values.

Regards,

-Adam

Thanks Adam,
Okay, so are you saying that subtle differences between each FET might cause just one of them to conduct slightly better and therefore reach OC tripping point before any other. Even if this was the case, I imagine you would need a large difference in RDSon to restrict total output current to just 17A. Maybe you are suggesting that rise and fall times are also slightly askew and therefore again we might load up one FET and not the other, but on an integrated circuit like this I would have thought this is very unlikely, and the datasheet also tells us the OC trip takes a minimum of 150nS. This is significantly longer than the switching transition time. So I doubt this is the issue. So what is?

Finally ....oh yeah....probably not...... I also see form the datasheet that in PBTL mode, the total output power graphs seem to exceed the values stated in the recommended settings. Not by much, but I don't need much. For example when driving 2ohm we see the output power figure rise up to over 650W at a voltage of 54V. This makes sense as in such a situation would should see over 21A through the P-Bridge. It also shows that at higher load impedances the Vdd can rise still higher seems like 57V.
So what do I make of this. well it suggests that the device can handle the slightly higher voltages and the absolute max settings suggest this is quite reasonable. But I suppose that power dissipation becomes the real concern. As the currents rise clearly the heat generated will become a big problem. Getting rid of this energy is I suspect where the real limits lie. Could you hint at if you agree ;)

Therefore the potential of a parallel parallel configuration would be great. Its not that I need 1200W RMS. What I need is cooler chips and much more headroom for reliability sake.

To be totally specific here is the exact problem. I am designing a PA system. The unit runs from batteries. Using Li-ion, and without nastly regulation, for efficiency sake, I have a battery voltage curve that can start around 58.8V when the cells are absolutely fully charged. Very shortly after running some power out of the cells. The nominal voltage falls to ~3.75V per cell and this drops the battery voltage to around 52.5V. I'm quite comfortable with the 52.5V part. Its switching it on that might be a problem. I am thinking on the idea of measuring the voltage using an A/D and then hard limiting the drive into the power amp. But I still need to be content that the 58.8V Vdd is not going to fry the device.

I have run them at 58V and a little higher, with limited output power all was fine. Only when I ramped up the power did I get flames.
So you can see why I'm battling.

Any further insight, much appreciated.
Aidan