TLV320AIC3254: TLV320AIC3254

Hi, Boris,

In order to get a beep output from the AIC3254, you need to have a couple things in mind. In first place, you need to select PRB_P25 as the the DAC processing block of the codec. The clock selection depends on the processing block required instructions and divider configurations. For this processing block, a 2.048MHz master clock may not be enough, so you will need to use the PLL to provide a valid clock for the device processing. In addition, you need to make sure the beep frequency is below Fs/4. Can you please share the system-level settings of your codec so I can help with the configuration of the device?, information like LDO use, clock frequency used, Digital audio format, desired beep frequency/duration and outputs used would be useful. 

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

Thanks, Diego, for response.

I thought that procedure for doing a beep should be quite simple, just to program 71-79 registers as it is written in the manual. I thought to use it just for initial testing of the AIC3254 chip. Seems, it is not very easy. Below are registers I have tried to program to get a beep. No success.

0x00 0x00 ////0 page
0x01 0x01 //reset
0x0b 0x81 //ndac=1
0x0c 0x81 //mdac=1
0x0d 0x00 //ocr=128
0x0e 0x80 //ocr=128
0x1b 0x00 ////i2s
0x78 0x19//prb _p25
0x00 0x01//page1
0x01 0x08////avdd disable
0x02 00///power control
0x0a 0x00///input common mode
0x0c 0x08//dac to hpl
0x0d 0x08//dac to hpr
0x03 0x00////ptm_p3/4
0x04 0x00////ptm_p3/4
0x09 0x30////power uo HPL and HPR

0x00 0x00 /////page 0 again

0x73 0x01///beep burst length
0x74 0x77///beep burst length
0x75 0x00///beep burst length
0x72 0x85///db
0x71 0x85///beep 0n
0x3f 0xd6///power up left and right channels
0x40 0x00 /////unmute volume control

I have only one clock input now which is MCLK = 2.048 MHz. Should I add BCLK as well? What the frequency should be there? Because it is not clear from the documentation, which CLK signals MUST be put as an input in order to form CODEC_CLK_IN.
Actually I am going to use beep procedure just an initial test of how register programming works.

As a real task I need to get audio signal on HPL and HPR using I2S data input from CC1350 host controller. Here appeared to be a new serious issue. In contrast to I2c, for I2S on CC1350 I did not find any i2s usage example, i2s.h library functions description. Implementing this protocol using only my own guesses takes too much time. Can you advice me an example and description on how to use i2s.h library on cc1350?

THanks in advance. Your advices on abovementioned issues would be very usefull.

Boris Shkarban.

Hi, Boris,

The AIC3254 is a complex device which requires initial programming and system-level constrains to operate properly. Depending on the device operation mode, you need to provide either a single MCLK (when the codec generates the I²S clocks) or all the I²S clocks. If your codec is the master of the I²S bus, you can provide a single MCLK and configure the codec to provide both bit clock and word clock. I would recommend you to take a look tot he AIC3254 CS GUI, which has some examples for the device general configuration. I can generate a code for you to try, but for that I need some information; can you please let me know what is the sampling rate you want to use in your system and if the codec will be the master or slave of the I²S bus?. 

Regarding the configuration of the CC1350 for I²S mode, I am afraid I will not be helpful as i'm not familiar with the device, so I would recommend you to contact my colleagues of the corresponding support forum.

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

Hi, Diego,

It would be very helpful if you would advice me a configuration code to configure AIC3254. If I will do that by the method of guess and try, it will take too much time, while I have deadline for that project end of September.

AIC3254 should be a slave, cc1350 will be a master, sending Audio stream over the I2S lines. Sampling rate is 16 KHz, the sample word length will be 16 bits, 

MCLK is provided from quarz henerator 2.048 MHz, WCLK 16 KHz will be provided, as I understand, from cc1350, BCLK=16000 Hz * 16 bits * 2 =512000 bit/sec will be provided from cc1350 as well.

AVDD and DVDD are 1.8 volt.

I2S protocol from cc1350 I have configured more or less, now I need to configure AIC3254.

please help,

Boris