TLV320AIC3254: Question to linked post which has been locked

Miguel Carvalho

Part Number: TLV320AIC3254

Hi Diego

I see the old post has been locked. Sorry for the delay in my response.

have compiled the entire register setup with some comments on the setup. Please could you review and let me know if you see anything alarming.

Please let me know if you would like me to provide or do anything else to the data.

REGNUM REGVAL (HEX)	Description	Comment
00 00	SET PAGE 0
01 01	GPIOisGenPurposeIN/OUT
1B 4C	Audio IF- DSP/32bits/BCLK OUT/ WCLK OUT/DOUT WILL NOT BE HIGH IMP	Is this a concern, does DOUT need to be high for miniDSP I/f?
0B 84	NDAC (OVERWRITTEN with MiniDSP Config)
0C 84	MDAC (OVERWRITTEN with MiniDSP Config)
0D 00	DAC OSR (OVERWRITTEN with MiniDSP Config) MSB
0E 20	DAC OSR (OVERWRITTEN with MiniDSP Config) LSB
1D 03	Audio IF- No Loop back/NoLoopBack/DefaultBitClockPolarity/BCLKDOwnCOdecDOwn/BDIV_CLKIN=ADC_MOD_CLK
1E 81	ClockSet-BCLKNDIVPoweredUP/1
3C 11	PRB SET (OVERWRITTEN with MiniDSP Config)
00 01	SET PAGE 1
01 08	Power Config Disable weak conn of AVDD with DVDD
02 21	DVDDldo-1.72/AVDD-1.77/AnalogBLCKSenabled/NoOVERcurrentDetection
0A 00	CommonMode-0.9V/HPRHPL=Common/LOLLOL=Common/PoweredAVDD/LDOIN1.5-1.95V
47 32	AnalogINQuickCharging =6.4ms
7B 01	Reference will power up in 40ms when analog blocks are powered up
14 05	HeadphoneDriver-2.0 TimeConstants
0E 08	LOL Routing - LeftDACReconFilter Routed to LOL
03 00	Playback-LeftDACtoHPLUsesClassAB
04 00	Playback-RightDACtoHPLUsesClassAB
10 00	HPLDriver Gain
11 00	HPR Driver Gain
12 00	LOL Driver Gain
13 00	LOR Driver Gain
00 00	SET PAGE 0
41 00	LEFTDACVOlume
42 00	RIGHTDACVOlume
3F D4	DAC-LeftUP/RightUP/LeftDACDataLeftChanAudioIFData/RightDACDataRightChanAudioIFData
40 00	DAC- PowDown=zero/AutoMuteDIsabled/LeftDacNotMuted/RightDacNotMuted/LeftRightIndepVol
00 01	SET PAGE 1
0C 08	HPLRouting-LeftDACtoHPL/IN1LtoHPL
0D 0A	HPRRouting-RightDACtoHPL/IN1RtoHPR
0F 08	LORRouting-RightDACtoLOR
09 3D	OutputDriver- All powered on Except MAL
00 00	SET PAGE 0
34 0C	GPIOisGenPurposeIN/OUT
04 03	LowPLLClockRange/MCLKinPLL/PLL=CODEC_CLKIN
05 B1	PLL P,P (OverWritten in MiniDSP Config)
06 14	PLL J,D (OverWritten in MiniDSP Config)
07 00	PLL J,D (OverWritten in MiniDSP Config)
08 00	PLL J,D (OverWritten in MiniDSP Config)
12 84	NADC(OverWritten in MiniDSP Config)
13 84	MADC(OverWritten in MiniDSP Config)
14 20	AOSR(OverWritten in MiniDSP Config)
3D 07	ADC PRB (OverWritten in MiniDSP Config)
56 00	LeftAGC =OFF (OverWritten in MiniDSP Config)
00 01	SET PAGE 1
3D 00	ADC PowerTUne=PTM_R4
33 00	MICBias=off
34 40	IN3L is routedto LEFt MICPGA20kREes
36 40	IN3R is routedto LEFt MICPGA20kREes
37 40	IN3R is routedto Right MICPGA20kREes
39 40	IN3L is routedto Right MICPGA20kREes
3B 00	LEFTMICPGA=0dB
3C 00	RightMICPGA=0dB
00 00	SET PAGE 0
51 C0	ADC-LeftADCup/RightADCup/GPIOmicIN/leftADCNotMIC/RightADCNotMIC/ADCVolCtrl1GainPerClockword
52 00	ADC-LeftADCunmuted/odB/Rightunmuted/odB
5E 62	LEftAGCSet (after SDV config)
5F 40	LEftAGCSet (after SDV config)
60 48	RightAGCSet (after SDV config)
61 00	RightAGCSet (after SDV config)
62 32	RightAGCSet (after SDV config)
63 05	RightAGCSet (after SDV config)
64 07	RightAGCSet (after SDV config)
53 00	LeftADCVolCtrl
54 00	RightADCVolCtrl



MINI DSP SETUP	Similar to previous Setup

00 08	SET to PAGE 8
08 00
09 B7
0A 98
0B 00
0C 7E
0D 90
0E D0
0F 00
10 7F
11 FF
12 FF
13 00
14 00
15 00
16 00
17 00
18 00
19 00
1A 00
1B 00
1C FF
1D FF
1E FF
1F 00
20 80
21 00
22 00
23 00
24 7F
25 FF
26 FF
27 00
28 40
29 00
2A 00
2B 00
2C 00
2D 00
2E 00
2F 00
30 FF
31 6B
32 00
33 00
34 FF
35 03
36 00
37 00
38 FC
39 C6
3A 00
3B 00
3C F5
3D 54
3E 00
3F 00
40 F9
41 64
00 50	SET TO PAGE 80
08 00
09 00
0A 00
0B 00
0C 00
0D 00
0E 00
0F 00
10 30
11 50
12 0A
6F 00
70 38
71 2C
72 1C
73 00
74 38
75 2C
76 2E
77 00
78 38
79 30
7A 20
7B 00
7C 38
7D 30
7E 2A
7F 00
00 51	Set to PAGE 81
08 38
09 34
0A 21
0B 00
0C 38
0D 34
0E 29
0F 00
10 38
11 38
12 22
13 00
14 38
15 38
16 28
17 00
18 38
19 3C
1A 25
1B 00
1C 38
1D 40
1E 2B
1F 00
20 38
21 40
22 1F
23 00
24 38
25 44
26 1E
27 00
28 38
29 44
2A 2C
2B 00
2C 38
2D 48
2E 1D
2F 00
30 38
31 48
32 2D
33 00
34 38
35 4C
36 23
37 00
38 38
39 4C
3A 27
3B 00
3C 38
3D 50
3E 24
3F 00
40 38
41 50
42 26
43 00
44 58
45 04
46 15
47 00
48 50
49 0C
4A 00
4B 00
4C 50
4D 00
51 00
52 00
53 00
54 38
55 17
56 FB
57 00
58 88
59 17
5A FE
5B 00
5C 00
5D 00
5E 00
5F 00
60 08
61 00
62 00
63 00
64 08
65 04
66 1A
67 00
68 00
69 00
6A 00
6B 00
6C 88
6D 03
6E FF
6F 00
00 2C	Set to page 44
08 FF
09 FF
0A FF
0B 00
0C 80
0D 00
0E 00
0F 00
10 7F
11 F7
12 00
13 00
14 80
15 09
16 00
17 00
18 7F
19 EF
1A 00
1B 00
1C 40
1D 00
1E 00
1F 00
20 7F
21 FF
22 FF
23 00
24 00
25 00
26 00
27 00
28 FF
29 F8
2A 00
2B 00
2C FF
2D D8
2E 00
2F 00
30 FF
31 F6
32 00
33 00
34 FE
35 BF
36 00
37 00
38 3A
39 D8
3A 00
3B 00
3C 00
3D 15
3E 00
3F 00
40 00
41 06
42 00
43 00
44 00
45 67
46 00
47 00
48 00
49 4F
4A 00
4B 00
4C 01
4D D5
4E 00
4F 00
50 24
51 89
52 00
53 00
54 FC
55 AB
56 00
57 00
58 FF
59 19
5A 00
5B 00
5C F3
5D E3
5E 00
5F 00
60 06
61 1E
62 00
63 00
64 00
65 00
66 4F
67 00
00 98	Set to page 152
08 00
09 00
0A 00
0B 00
0C 00
0D 00
0E 00
0F 00
10 08
11 00
12 00
13 00
14 08
15 04
16 01
12 26
13 00
14 38
15 24
16 20
17 00
18 38
19 28
1A 28
1B 00
1C 38
1D 28
1E 1E
1F 00
20 38
21 2C
22 22
23 00
24 38
25 2C
26 24
27 00
28 38
29 30
2A 23
2B 00
2C 38
2D 34
2E 29
2F 00
30 38
31 34
32 1D
33 00
34 38
35 38
36 27
37 00
38 38
39 38
3A 1F
3B 00
3C 38
3D 3C
3E 25
3F 00
40 38
41 3C
42 21
43 00
44 00
45 00
46 00
47 00
48 50
49 04
4A 01
4B 00
4C 30
4D 40
4E 14
4F 00
50 38
51 40
52 07
53 00
54 20
55 08
56 2B
57 00
58 38
59 44
5A 12
5B 00
5C 38
5D 44
5E 09
5F 00
60 38
61 48
62 0E
63 00
64 38
65 48
66 0D
67 00
68 38
69 4C
6A 0A
6B 00
6C 38
6D 4C
6E 11
6F 00
70 38
71 50
72 13
73 00
74 38
75 50
76 08
77 00
78 38
79 54
7A 0F
7B 00
7C 38
7D 54
7E 0C
7F 00
20 20
21 08
22 15
23 00
24 38
25 44
26 27
27 00
28 38
29 44
2A 1E
2B 00
2C 38
2D 48
2E 23
2F 00
30 38
31 48
32 22
33 00
34 38
35 4C
36 1F
37 00
38 38
39 4C
3A 26
3B 00
3C 38
3D 50
3E 28
3F 00
40 38
41 50
42 1D
43 00
44 38
45 54
46 24
47 00
48 38
49 54
4A 21
4B 00
4C 38
4D 58
4E 25
4F 00
50 38
51 58
52 20
53 00
54 00
55 00
56 00
57 00
58 50
59 04
5A 01
5B 00
5C 00
5D 00
5E 00
5F 00
60 00
61 00
62 00
63 00
64 20
65 08
66 2A
67 00
68 30
69 5F
6A FB
6B 00
6C 00
6D 00
6E 00
6F 00
70 38
71 03
72 FB
73 00
74 88
75 17
76 FE
77 00
78 30
79 18
7A 00
7B 00
7C 30
7D 18
7E 01
7F 00
00 9B	Set to Page 155
08 00
09 00
0A 00
0B 00
0C 20
0D 00
0E 02
0F 00
10 20
11 00
12 17
13 00
14 10
15 00
16 16
17 00
18 10
19 04
1A 2B
1B 00
1C 88
1D 03
1E FF
1F 00
00 00	Set to page 0	These are the only possible registers that could overwrite the configuration. I dont see any issue with the ones that are?
3C 00
3D 00
11 02
17 01
0F 01
10 00
15 01
16 00
05 91
06 08
07 00
08 00
04 03
0C 88
0D 00
0E 20
12 02
13 88
14 20
0B 82
52 00
53 00
54 00

Best Regards

Miguel Carvalho

over 6 years ago

0 Diego Melendez over 6 years ago

TI__Guru 57800 points

Hi, Miguel,

Thanks for the information. I assume this is a crude dump of the codec configuration, where all the registers listed reflects the codec conditions during normal operation, right?. I noted that only the miniDSP coefficients are added to the commented code, which is the one you use to configure the device initially. As I pointed before, there are certain registers which should be written to the device before the miniDSP code is loaded, and from the code shared some of them are not configured. Can you please look at the code I shared on the locked post (From Dec 3), and make sure the registers which are not commented there and that are missing on your code are added to the registers you are sharing?

Best Regards,

-Diego Meléndez López
Audio Applications Engineer

0 Miguel Carvalho over 6 years ago in reply to Diego Melendez

Prodigy 170 points

Hi Diego

Thank you for your reply

Yes essentially this is a crude dump. I sniffed the I2C line to ensure all that I expect to be set it set.

I assume you are referring to these registers being commented?
reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8
reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8
reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
reg[ 0][ 13] = 0x00 ; DOSR = 32 (MSB)
reg[ 0][ 14] = 0x20 ; DOSR = 32 (LSB)
reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
reg[ 0][ 19] = 0x88 ; MADC = 8, divider powered on
reg[ 0][ 20] = 0x20 ; AOSR = 32
reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on

If I look at the dump they are all configured. Some are configured after the miniDSP configuration. Are you saying that they should be set before any miniDSP config?

Best Regards
Miguel

0 Miguel Carvalho over 6 years ago in reply to Miguel Carvalho

Prodigy 170 points

Hi Diego,

I tried to put those PLL configuration registers before the miniDSP COnfig with no difference. Maybe I misunderstood what you were saying?

0 Diego Melendez over 6 years ago in reply to Miguel Carvalho

TI__Guru 57800 points

Hi, Miguel,

I was not referring to the PLL registers specifically, I was referring to other registers such as the ones located below the Signal Processing Settings section on the code I pointed before. I would like to load your register settings on my EVM and double check the configuration of the device in the bench. I won't have access to the EVM today, but I expect to provide some results tomorrow.

Best Regards,

-Diego Meléndez López
Audio Applications Engineer

0 Miguel Carvalho over 6 years ago in reply to Diego Melendez

Prodigy 170 points

Hi Diego

Just a follow up, have you had the chance to run it in your EVM?

Best Regards
Miguel Carvalho

0 Diego Melendez over 6 years ago in reply to Miguel Carvalho

TI__Guru 57800 points

Hi Miguel,

Sorry for the delayed response. I actually did some quick tests on the EVM, and after loading the registers you shared, the EVM is not working, I was planning to perform more tests before giving you a response, I suspect that the Signal Processing registers I pointed out before are not properly configured on your code, but haven't verified it as unfortunately I haven't find the required time to do a detailed debug. Can you please check the registers I pointed out, and add them to your code to verify if there is any improvement?. I'll see if I could keep with the testing, I should be able to provide some results by tomorrow.

Best Regards,

-Diego Meléndez López
Audio Applications Engineer

0 Miguel Carvalho over 6 years ago in reply to Diego Melendez

Prodigy 170 points

HI Diego,

Thank you very much for your response and I hope you find some additional time to perform a detailed debug.

I am a bit confused when it comes to the registers you pointed out. If you could explicitly copy the settings you are referring to then I will try it out. I will also give you some time as you are more likely to find the issue on your side.

Best Regards

Miguel Carvalho

0 Diego Melendez over 6 years ago in reply to Miguel Carvalho

TI__Guru 57800 points

Hi, Miguel,

I am attaching the System settings code I mentioned before. Please review it and make sure the Signal Processing Settings are included in your code. Also, I noted that the ADCs are turned ON in your code before loading the miniDSP coefficients. Please note that the ADCs should be powered ON after all the coefficients are written to the miniDSP, otherwise the coefficients will not be loaded. This happens because once the ADC is ON, the coefficient-register access is changed from the I²C interface to the miniDSP engine, entering normal operation mode. I recall moving the ADC power register to the end of the code without success, but please try it.

Best Regards,

-Diego Meléndez López
Audio Applications Engineer

Fullscreen SystemSettingsCode-3254.txt Download

;-----------------------------------------------------------------------------------
; Software Reset
;-----------------------------------------------------------------------------------
reg[ 0][ 1] = 0x01 ; Initialize the device through software reset
reg[254][ 0] = 0x0a ; Delay 10ms

;-----------------------------------------------------------------------------------
; Configure Power Supplies
;-----------------------------------------------------------------------------------
%%if (%%prop(TargetBoard) == 2)
; AIC3254EVM-U specific configuration

;reg[ 1][ 2] = 0xa9 ; Power up AVDD LDO
;reg[ 1][ 1] = 0x08 ; Disable weak AVDD to DVDD connection
;reg[ 1][ 2] = 0xa1 ; Enable Master Analog Power Control, AVDD LDO Powered

%%else
; AIC3254EVM-K specific configuration 
reg[ 1][ 1] = 0x08 ; Disable weak AVDD to DVDD connection
reg[ 1][ 2] = 0x00 ; Enable Master Analog Power Control

%%endif

reg[ 1][ 71] = 0x32 ; Set the input power-up time to 3.1ms 
reg[ 1][123] = 0x01 ; Set REF charging time to 40ms (automatic)
reg[254][ 0] = 0x28 ; Delay 40ms for REF to Power Up

;-----------------------------------------------------------------------------------
; Load miniDSP Code
;-----------------------------------------------------------------------------------
PROGRAM_ADC ; miniDSP_A coefficients and instructions 
;PROGRAM_DAC ; miniDSP_D coefficients and instructions

;-----------------------------------------------------------------------------------
; Signal Processing Settings
;-----------------------------------------------------------------------------------
;reg[ 0][ 60] = 0x00 ; Use miniDSP_D for signal processing
reg[ 0][ 61] = 0x00 ; Use miniDSP_A for signal processing

%%if ("%%prop(FrameworkType)" == "AIC3254App8x4x") 
reg[ 0][ 17] = 0x08 ; 8x Interpolation
reg[ 0][ 23] = 0x04 ; 4x Decimation
%%endif

%%if ("%%prop(FrameworkType)" == "AIC3254App4x2x") 
reg[ 0][ 17] = 0x04 ; 4x Interpolation
reg[ 0][ 23] = 0x02 ; 2x Decimation
%%endif

%%if ("%%prop(FrameworkType)" == "AIC3254App2x1x") 
reg[ 0][ 17] = 0x02 ; 2x Interpolation
reg[ 0][ 23] = 0x01 ; 1x Decimation
%%endif

;IDAC = %%prop(miniDSP_D_Cycles)
IADC = %%prop(miniDSP_A_Cycles)

%%if (%%prop(miniDSP_A_Adaptive) == 1)
reg[ 8][ 1] = 0x04 ; adaptive mode for ADC
%%endif

%%if (%%prop(miniDSP_D_Adaptive) == 1)
;reg[ 44][ 1] = 0x04 ; adaptive mode for DAC
%%endif

;-----------------------------------------------------------------------------------
; Clock and Interface Configuration
;-----------------------------------------------------------------------------------
; USB Audio supports 8kHz to 48kHz sample rates
; An external audio interface is required for 88.2kHz to 192kHz sample rates
;-----------------------------------------------------------------------------------
%%if (%%prop(SampleRate) == 176400 || %%prop(SampleRate) == 192000)
reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8
reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8
reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
reg[ 0][ 13] = 0x00 ; DOSR = 32 (MSB)
reg[ 0][ 14] = 0x20 ; DOSR = 32 (LSB)
reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off 
reg[ 0][ 19] = 0x88 ; MADC = 8, divider powered on
reg[ 0][ 20] = 0x20 ; AOSR = 32
reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on

%%endif

%%if (%%prop(SampleRate) == 88200 || %%prop(SampleRate) == 96000)
reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8
reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8
reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
reg[ 0][ 13] = 0x00 ; DOSR = 64 (MSB)
reg[ 0][ 14] = 0x40 ; DOSR = 64 (LSB)
reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
reg[ 0][ 19] = 0x88 ; MADC = 8, divider powered on
reg[ 0][ 20] = 0x40 ; AOSR = 64
reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on
%%endif

%%if (%%prop(SampleRate) == 44100 || %%prop(SampleRate) == 48000)
reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8
reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8
reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
reg[ 0][ 13] = 0x00 ; DOSR = 128 (MSB)
reg[ 0][ 14] = 0x80 ; DOSR = 128 (LSB)
reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
reg[ 0][ 19] = 0x88 ; MADC = 8, divider powered on
reg[ 0][ 20] = 0x80 ; AOSR = 128
reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on
%%endif

%%if (%%prop(SampleRate) == 32000)
reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8
reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8
reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
reg[ 0][ 13] = 0x00 ; DOSR = 192 (MSB)
reg[ 0][ 14] = 0xc0 ; DOSR = 192 (LSB)
reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
reg[ 0][ 19] = 0x8c ; MADC = 12, divider powered on
reg[ 0][ 20] = 0x80 ; AOSR = 128
reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on
%%endif

%%if (%%prop(SampleRate) == 22050 || %%prop(SampleRate) == 24000)
reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8
reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8
reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
reg[ 0][ 13] = 0x01 ; DOSR = 256 (MSB)
reg[ 0][ 14] = 0x00 ; DOSR = 256 (LSB)
reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
reg[ 0][ 19] = 0x90 ; MADC = 16, divider powered on
reg[ 0][ 20] = 0x80 ; AOSR = 128
reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on
%%endif

%%if (%%prop(SampleRate) == 16000)
reg[ 0][ 5] = 0x91 ; P=1, R=1, J=24
reg[ 0][ 6] = 0x18 ; P=1, R=1, J=24
reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
reg[ 0][ 13] = 0x01 ; DOSR = 384 (MSB)
reg[ 0][ 14] = 0x80 ; DOSR = 384 (LSB)
reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
reg[ 0][ 19] = 0x98 ; MADC = 24, divider powered on
reg[ 0][ 20] = 0x80 ; AOSR = 128
reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on
%%endif

%%if (%%prop(SampleRate) == 11025)
reg[ 0][ 5] = 0x91 ; P=1, R=1, J=16
reg[ 0][ 6] = 0x10 ; P=1, R=1, J=16
reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
reg[ 0][ 13] = 0x02 ; DOSR = 512 (MSB)
reg[ 0][ 14] = 0x00 ; DOSR = 512 (LSB)
reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
reg[ 0][ 19] = 0xa0 ; MADC = 32, divider powered on
reg[ 0][ 20] = 0x80 ; AOSR = 128
reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on
%%endif

%%if (%%prop(SampleRate) == 8000)
reg[ 0][ 5] = 0x91 ; P=1, R=1, J=24
reg[ 0][ 6] = 0x18 ; P=1, R=1, J=24
reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
reg[ 0][ 13] = 0x03 ; DOSR = 768 (MSB)
reg[ 0][ 14] = 0x00 ; DOSR = 768 (LSB)
reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
reg[ 0][ 19] = 0xb0 ; MADC = 48, divider powered on
reg[ 0][ 20] = 0x80 ; AOSR = 128
reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on
%%endif



;-----------------------------------------------------------------------------------
; ADC Channel Configuration
;-----------------------------------------------------------------------------------
reg[ 1][ 51] = 0x40 ; Mic Bias enabled, Source = Avdd, 1.25V

%%if (%%prop(TargetBoard) == 2)
; AIC3254EVM-U specific configuration
reg[ 1][ 52] = 0x10 ; Route IN2L to LEFT_P with 10K input impedance
reg[ 1][ 54] = 0x40 ; Route CM1L to LEFT_M with 10K input impedance
reg[ 1][ 55] = 0x10 ; Route IN2R to RIGHT_P with 10K input impedance

%%else
; AIC3254EVM-K specific configuration
reg[ 1][ 52] = 0x40 ; Route IN1L to LEFT_P with 10K input impedance
reg[ 1][ 54] = 0x40 ; Route CM1L to LEFT_M with 10K input impedance
reg[ 1][ 55] = 0x40 ; Route IN1R to RIGHT_P with 10K input impedance

%%endif

reg[ 1][ 57] = 0x40 ; Route CM1R to RIGHT_M with 10K input impedance
reg[ 1][ 59] = 0x00 ; Enable MicPGA_L Gain Control, 0dB
reg[ 1][ 60] = 0x00 ; Enable MicPGA_R Gain Control, 0dB
reg[ 0][ 81] = 0xc0 ; Power up LADC/RADC
reg[ 0][ 82] = 0x00 ; Unmute LADC/RADC

;-----------------------------------------------------------------------------------
; DAC Channel Configuration
;-----------------------------------------------------------------------------------
;reg[ 1][ 20] = 0x25 ; De-pop: 5 time constants, 6k resistance
;reg[ 1][ 12] = 0x08 ; Route LDAC to HPL
;reg[ 1][ 13] = 0x08 ; Route RDAC to HPR
;reg[ 1][ 14] = 0x08 ; Route LDAC to LOL
;reg[ 1][ 15] = 0x08 ; Route LDAC to LOR
;reg[ 0][ 63] = 0xd4 ; Power up LDAC/RDAC w/ soft stepping
;reg[ 1][ 16] = 0x00 ; Unmute HPL driver, 0dB Gain
;reg[ 1][ 17] = 0x00 ; Unmute HPR driver, 0dB Gain
;reg[ 1][ 18] = 0x00 ; Unmute LOL driver, 0dB Gain
;reg[ 1][ 19] = 0x00 ; Unmute LOR driver, 0dB Gain
;reg[ 1][ 9] = 0x3c ; Power up HPL/HPR and LOL/LOR drivers
;reg[ 0][ 64] = 0x00 ; Unmute LDAC/RDACMi

0 Miguel Carvalho over 6 years ago in reply to Diego Melendez

Prodigy 170 points

Hi Diego

The Signal Processing Settings are all there.

And I also tried only powering the ADCs ON after the miniDSP Coefficients with no success.

I hope you are able to find some time to try something on yours side.

Best Regards
Miguel Carvalho

Audio

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TLV320AIC3254: Question to linked post which has been locked

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