PCM3002: PCM3002

shih hanro

Prodigy 70 points

Part Number: PCM3002
Other Parts Discussed in Thread: TLV320AIC3204, TLV320AIC3104

i use PCM3002 to test audio

1: the test block is showed in the below

all power input pin is 3.3V

But Vref1 =3.3V

Vref2= 0V

is this correct?

2: i also give signal to PCM 3002

1KHz sine wave ==> to Vin

1.SystemCLK=4.096MHz

2.LRCIN=8KHz

3.BCKIN=256Khz

but No Dout ?

what's wrong in this operation

over 5 years ago

0 Steve-Wilson over 5 years ago

TI__Mastermind 30100 points

Shih,

Did you program the registers? if so, please send your register configuration.
-Steve Wilson

0 shih hanro over 5 years ago in reply to Steve-Wilson

Prodigy 70 points

HI steve

No, I don' program any register

BRS

shih

0 Steve-Wilson over 5 years ago in reply to shih hanro

TI__Mastermind 30100 points

Shih,

You should program the registers.

best regards,
-Steve Wilson

0 shih hanro over 5 years ago in reply to Steve-Wilson

Prodigy 70 points

HI steve

1 : The default values in the datasheet seem to be OK for audio ADC test.

What values of these register to program for audio ADC test?

2: system clock = 256 * fs

if fs=32KHz , system clock = 8.192MHz

butI don't know how to choose the BCK's value ?

Have any equations?

BRS

shih

0 Steve-Wilson over 5 years ago in reply to shih hanro

TI__Mastermind 30100 points

can you remove power, and put a oscilloscope probe on the dout, with the trigger set to single, then turn the device on, and bring it out of reset.

does the DOUT ever have data on it? even one cycle?

best regards,
-Steve Wilson

0 shih hanro over 5 years ago in reply to Steve-Wilson

Prodigy 70 points

HI steve

we using 3 function generator to give system CLK &LRCIN/BCKIN

We found PCM dout will be toggled as the below table

In the datasheet , we have the LCKin[fs] relation.

But i want to know the BCKin equation , how to get it?

Thanks

item	System CLK	Fs=LCKin	BCKin=system/4	VinR&L	PCM dout Data (O/X)
1	8.192MHz	32KHz	2.048MHz	1k squre wave	O
2	12.288MHz	48KHz	3.072MHz	1k squre wave	O
3	18.432MHz	48KHz	4.608MHz	1k squre wave	O
4	24.576MHz	48KHz	6.144MHz	1k squre wave	O
5	12.288MHz	32KHz	3.072MHz	1k squre wave	O
6	16.384MHz	32KHz	4.096MHz	1k squre wave	O

0 Steve-Wilson over 5 years ago in reply to shih hanro

TI__Mastermind 30100 points

Shih,

are you syncing the function generators? The clocks must be synchronous.

-steve

0 Steve-Wilson over 5 years ago in reply to Steve-Wilson

TI__Mastermind 30100 points

Shih,

I never heard back from you. Are the function generators synchronized? the clocks must be in sync, if they are not, if the BCLK and Fsync are drift too much, the codec will have issues.

best regards,
-Steve Wilson

0 shih hanro over 5 years ago in reply to Steve-Wilson

Prodigy 70 points

HI steve

Yes, the function generators are sync

shih

0 shih hanro over 5 years ago in reply to Steve-Wilson

Prodigy 70 points

HI steve

the function generators are sync .

shih

0 shih hanro over 5 years ago in reply to shih hanro

Prodigy 70 points

i see the attached document

20bit data

CPLD input clk=12.288
sampling rate fs=8khz

codec sysCLK=2.048MHz

LRCIN=fs=8khz

BCLKin=CODE_SYSCLK/4=512K ?

How to get 4?

example.pdf

0 Steve-Wilson over 5 years ago in reply to shih hanro

TI__Mastermind 30100 points

Shih,

BCLK = 512khz when LRCIN is 8khz is not possible.
There is a limit 64BLCK/LRCIN on the PCM3002/3003

Have you considered using a newer device? perhaps the TLV320AIC3204 or TLV320AIC3104?

best regards,
-Steve Wilson

0 SHY over 5 years ago in reply to Steve-Wilson

Prodigy 160 points

Hi Steve,

What is the meaning of 64BCLK/LRCIN?

In the p.19, we see following description :

The PCM3002/3003 can accept 32, 48, or 64 bit clocks (BCKIN) in one clock of LRCIN. Only the 16-bit data
format can be selected when 32-bit clocks/LRCIN are applied.

Following clock combination is possible?

1.SystemCLK=4.096MHz

2.LRCIN=8KHz

3.BCKIN=256Khz

thank you.
SHY

0 Steve-Wilson over 5 years ago in reply to SHY

TI__Mastermind 30100 points

SHY,

64BCLK/LRCIN means that for every 1 cycle of LRCIN there can be a maximum of 64BCLK cycles.

There are two data slots in 1 cycle of LRCIN, so this means that each Data slot has a maximum of 32BCLKs.
The reason that 32bclks/LRCIN can only be used with 16-Bit data, is because 24bit data wouldn't fit in a 16bit slot.

The clock combination You've shown has a bclk/LRCIN ratio of 32 so it can be used for 16bit Data only.

best regards,
-Steve Wilson

Audio

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PCM3002: PCM3002