Precisely what happens when RESET is set LOW, and LOW to HIGH, HIGH to LOW ?
The datasheet states: "9.4.1.8 Device Reset. Asserting RESET low initiates the device ramp down. The output FETs go into a Hi-Z state AFTER the ramp down is complete."
What exactly is "ramp down" and what is or isn't operating during that time ?
Is there any way to control the "ramp down" timing ?
The datasheet also states: "11.3 Powering Down. The TPA3255 does not require a power-down sequence. The device remains fully operational as long as the gate-drive supply (GVDD_X) voltage and VDD voltage are above the under-voltage protection (UVP) voltage threshold (8,7V). Is this true even if RESET = LOW ? Although not specifically required, it is a good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks by initiating a controlled ramp down sequence of the output voltage.
Does keeping RESET = LOW when powering down avoid this "ramp down".
