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TAS2559: PLL and Clocking configuration

Part Number: TAS2559

As there is no description of the clock tree for the TAS2559, I have tried to make a description based on information I have obtained from various sources.
See drawing below.

The description is not complete, among other things I'm missing all PLL rules, clock ranges and limitations.

Could you please provide me the missing information ? - Thanks

In relation to the PLL configuration I need to know the definition of following registers:

B100P0R1
B100P0R2
B100P0R34
B100P0R42
B100P0R43
B100P0R44

-and I also need to know how to specify DOSR.

Doing configuration of the PLL and clock registers I've noticed that some unspecified interrupt sources are set in the INT_DET_1 and INT_DET_2 registers.

In INT_DET_1 (B0P0R104) bit 5 (reserved) is set. I think this bit means "CLK HALTED". Please confirm and describe what it means (which clock is halted).
In INT_DET_2 (B0P0R108) bit 1 (reserved) is set. Please describe this bit.

TAS2559 Clock Tree (draft):

       GPI(O)      OSC
         |          |
      +--+----------+--+
      |    PLL MUX     | B0P1R116 selects clk source
      +-------+--------+
              |
      +-------+--------+ B100P0R27 sets P (1-64)
      |  PLL (J.D/P)   | B100P0R28 sets J (1-64)
      +-----+----------+ B100P0R29 sets D (MSB)
            |            B100P0R30 sets D (LSB)   
            |
  GPI(O)    |
    |       |
 +--+-------+--+
 |  NDIV MUX   | B0P1R115 selects clk src
 +------+------+
        |
 +------+------+
 |     NDIV    | B100P0R32 sets NDIV ratio (1-127)
 +------+------+
        |               ?
        +-----------+   |
        |    +------+---+--+
        |    |   DSP MUX   | B100P0R31 selects clk source
        |    +------+------+
        |           |
        |           +----> DSP clk
        |
        | DAC_CLK
 +------+------+
 |     MDIV    | B100P0R33 sets MDIV ratio (1-127)
 +------+------+
        | DAC_MOD_CLK
 +------+------+
 |     DOSR    | B?P?R? sets DOSR ratio (1-?)
 +------+------+
        | DAC_FS

Best Regards

Frank Rolsted Jensen

  • Hi, Frank,

    I'm taking a look at this. I will answer as soon as possible.

    Best regards,
    Luis Fernando Rodríguez S.

  • Frank,

    This is the information that I found related to the missing settings:

    B100P0R1: DAC Interpolation Ratio outside DSP.

    D7-D0

    Reset value

    8

    0 Interpolation Ratio outside DSP = 256
    1 Interpolation Ratio outside DSP = 1
    2 Interpolation Ratio outside DSP = 2
    253 Interpolation Ratio outside DSP = 253
    254 Interpolation Ratio outside DSP = 254
    255 Interpolation Ratio outside DSP = 255


    B100P0R2: ADC Decimation Ratio outside DSP.

      D7-D6

    Reset Value:

    0

    All Values Reserved
    D5-D0

    Reset Value:

    16

    0 Decimation Ratio outside DSP = 64
    1 Decimation Ratio outside DSP = 1
    2 Decimation Ratio outside DSP = 2
    37 Decimation Ratio outside DSP = 37
    38 Decimation Ratio outside DSP = 38 (maximum ratio supported for Isense/Vsense)
    39 Decimation Ratio outside DSP = 39 (supported only for PDM audio input)
    40 Decimation Ratio outside DSP = 40 (supported only for PDM audio input)
    41 Decimation Ratio outside DSP = 41 (supported only for PDM audio input)
    42 Decimation Ratio outside DSP = 42 (supported only for PDM audio input)
    43 Decimation Ratio outside DSP = 43 (supported only for PDM audio input)
    44 Decimation Ratio outside DSP = 44 (supported only for PDM audio input)
    45 Decimation Ratio outside DSP = 45 (supported only for PDM audio input)
    Others Not supported 


    B100P0R34: ADC MADC_VAL

      D7 Reset: 0 All values Reserved don't write any value other than reset value.
    D6-D3

    Reset:

    2

    0 ADC divider MADC pre = 16
    1 ADC divider MADC pre = 1
    2 ADC divider MADC pre= 2
    14 ADC divider MADC pre= 14
    15 ADC divider MADC pre= 15
    D2-D0

    Reset:

    0

    0 ADC divider MADC final = 8  (this divider configuration is used only if below register-42 D7-D6 = "11")
    1 ADC divider MADC final = 1
    2 ADC divider MADC final = 2
    6 ADC divider MADC final = 6
    7 ADC divider MADC final = 7


    B100P0R42: Force PWR DN ISNS Div Register

      D7-D6   

    Reset:

    0

    0 Isense div and MADC final divider configure auto assuming MADC pre-divider clock freq = 512*Fs where Fs is 48khz or 44.1khz
      1 Isense div and MADC final divider configure auto assuming MADC pre-divider clock freq = 256*Fs where Fs is 48khz or 44.1khz
      2 Reserved
      3 Reserved
      D5 

    Reset:

    0 isns_div2_bypass = 0 (this  configuration is used only if register-42 D7-D6 = "11")
      1 isns_div2_bypass = 1 (this  configuration is used only if register-42 D7-D6 = "11")
      D4 

    Reset:

    0 adc_mod_clk_del = 1cycle (this  configuration is used only if register-42 D7-D6 = "11")
      1 adc_mod_clk_del = 0.5cycle (this  configuration is used only if register-42 D7-D6 = "11")


    B100P0R43: Ramp Clk Div Factor MSB

      D7-D3

    Reset:

    0

    All Values Reserved
    D2-D0

    Reset:

    0

    0 ramp_clk_div_factor_msb

      

    B100P0R44: Ramp Clk Div Factor LSB

    D7-D0

    Reset:

    128

    ramp_clk_div_factor_lsb

     

    ( ... additional information in next post ...)

  • (... continued ...)

    DOSR specification:

    It seems that this device doesn't have manual DOSR configuration. Instead of it, the Book 0, Page 0, Register 47 (0x2F), Bits D1-D0 are used to select the sampling rate and calculate the OSR ratio. When a value lower than 48KHz is selected, it is also necessary to disable the DMA deglitch logic (Book 0, Page 0, Register 45 (0x2D), Bit D6 as '1'. I don't understand why this value is also marked as reserved, but I include the details below:

    D6 

    Reset:

    0 Don't bypass DMA deglitch logic.
    1 Bypass DMA deglitch logic. This makes sure that input DMA request to DSP are given only after 8 input dma clocks(asi dma or pdm dma based on mode) are stable.

    In INT_DET_1 (B0P0R104) bit 5 (reserved) is set. I think this bit means "CLK HALTED". Please confirm and describe what it means (which clock is halted).

    This Bit is related to the Boost Over-current detection:

    D5 Reset: 0  0 Boost Over-current is not detected
      1 Boost Over-current is detected

    In INT_DET_2 (B0P0R108) bit 1 (reserved) is set. Please describe this bit.

    This bit is related to the direct memory access request flag. It is marked as reserved since it is related to the internal DSP operation. 

    D1 Reset: 0

    dma_req_stable_flag (0)

    dma_req_unstable_flag (1)

    I hope this helps you. Please let me know if you require additional information on this. We will be glad to help you.

    Best regards,
    Luis Fernando Rodríguez S.

  • Hi Luis,

    Thanks, very much appreciated.

    I'll try to use the new register definitions to configure the codec.

    Although DOSR is set indirectly by setting the sample rate it must have some impact on the PLL/NDIV/MDIV settings. I guess DAC_MOD_CLK must be within a certain range and probably also a multiple of 64.

    Best Regrds
    Frank Rolsted Jensen

  • Hi, Frank,

    I agree. It seems that for 48KHz the ratio between DAC_MOD_CLK and fs must be 64 as you mentioned. Let me find for more information about the ratio for the rest of frequencies. I will answer in few moments.

    Best regards,
    Luis Fernando Rodríguez S.

  • Hi, Frank,

    You may use a reference of DAC_MOD_CLK = 3.072MHz in order to determine the ratio as shown in the information below:

    8KHz -> Ratio = 384
    16KHz -> Ratio = 192
    48KHz -> Ratio = 64
    96KHz -> Ratio = 32

    Please let me know if you have additional questions or comments on this.

    Have a good day!

    Best regards,
    Luis Fernando Rodríguez S.

  • Luis,

    I'm trying to configure the codec to run with a sample rate at 8KHz/16bit in mono mode (only one PCM channel).

    I'm using following configuration:

    • DSP mode 1 (register B0P0R34)
    • sample rate set to 8KHz in register B0P047 (ASI_CTRL_2)
    • ASI1 format set to MonoPCM or DSP in register B0P1R1 (ASI_FORMAT)
    • ASI input set to MonoPCM (in monoPCM mode) and Left channel (in DSP mode) in register B0P02A (ASI_CTRL_1)
    • the DMA deglitch logic is disabled (as you suggested)
    • DAC_MOD_CLK = 3.072MHz
    • Codec is bclk/wclk master

    It does not work and it seems to me that the specification of the sample rate is ignored by the DSP.

    Do you have an example showing how to configure the codec to run DSP Mode1/8KHz/16bit/1ch ?

    /Frank 

  • (continued)

    However, if I set the "DAC Interpolation Ratio outside DSP" register (B100P0R1) to 48 (8 (default) * 6 (48/8) ) it seems to work (in MonoPCM mode).

    Please describe how to use the Interpolation register in different configurations - thanks.

    /Frank 

  • Hi, Frank,

    Thank you for pointing out this situation.

    I have been searching for more information and it seems that this DAC Interpolation Ratio outside DSP is the "DOSR" value that you were asking in previous posts. We tested this solution on our EVM and it coincides with a divider value like DOSR in your clocking tree. I think that you should get the same results if you leave this Interpolation Ratio in default value and modify some other clock dividers to get the same divider results.

    I hope this makes sense. Please let me know if you have additional questions or comments.

    Best regards,
    Luis Fernando Rodríguez S.