As there is no description of the clock tree for the TAS2559, I have tried to make a description based on information I have obtained from various sources.
See drawing below.
The description is not complete, among other things I'm missing all PLL rules, clock ranges and limitations.
Could you please provide me the missing information ? - Thanks
In relation to the PLL configuration I need to know the definition of following registers:
B100P0R1
B100P0R2
B100P0R34
B100P0R42
B100P0R43
B100P0R44
-and I also need to know how to specify DOSR.
Doing configuration of the PLL and clock registers I've noticed that some unspecified interrupt sources are set in the INT_DET_1 and INT_DET_2 registers.
In INT_DET_1 (B0P0R104) bit 5 (reserved) is set. I think this bit means "CLK HALTED". Please confirm and describe what it means (which clock is halted).
In INT_DET_2 (B0P0R108) bit 1 (reserved) is set. Please describe this bit.
TAS2559 Clock Tree (draft):
GPI(O) OSC
| |
+--+----------+--+
| PLL MUX | B0P1R116 selects clk source
+-------+--------+
|
+-------+--------+ B100P0R27 sets P (1-64)
| PLL (J.D/P) | B100P0R28 sets J (1-64)
+-----+----------+ B100P0R29 sets D (MSB)
| B100P0R30 sets D (LSB)
|
GPI(O) |
| |
+--+-------+--+
| NDIV MUX | B0P1R115 selects clk src
+------+------+
|
+------+------+
| NDIV | B100P0R32 sets NDIV ratio (1-127)
+------+------+
| ?
+-----------+ |
| +------+---+--+
| | DSP MUX | B100P0R31 selects clk source
| +------+------+
| |
| +----> DSP clk
|
| DAC_CLK
+------+------+
| MDIV | B100P0R33 sets MDIV ratio (1-127)
+------+------+
| DAC_MOD_CLK
+------+------+
| DOSR | B?P?R? sets DOSR ratio (1-?)
+------+------+
| DAC_FS
Best Regards
Frank Rolsted Jensen