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Original question:

TLV320AIC3262 I2S bypassing

TLV320AIC3212: Questions related to routing audio from one ASI interface to the other.

Mikhail Chusov
Prodigy 20 points
Part Number: TLV320AIC3212


Hello. I have a few questions about routing signals between ASI interfaces on TLV320AIC3212 codec:

1. What is the difference between "DOUT1 from ASI2 Data Input (Pin-to-Pin Loopback)" (configured in Book 0 / Page 4 / Register 15: Audio Serial Interface 1, Data Output - 0x00 / 0x04 / 0x0F (B0_P4_R15)) and "ASI2-to-ASI1 loopback" (configured in Book 0 / Page 4 / Register 7: Audio Serial Interface 1, ADC Input Control - 0x00 / 0x04 / 0x07 (B0_P4_R7))?

2. I want to route audio from ASI1 input to ASI2 output, but these two interfaces have different bit clock frequencies and bit depth. Will the signal be transformed from format of one ASI to the format of other ASI?

3. Similar question. Routing ASI1 input to ASI2 output. But also sampling frequencies of these interfaces (word clock frequencies) are different. Will the codec execute resampling in this case?

3. I want to route audio from ASI1 to ASI2. Frequencies and format of audio samples should be the same. But codec acts as slave in both interfaces. Will this configuration work? How will slight differences in clocks of the two masters be handled by codec (clock generators always have slight different frequencies even when configured in the same way)?

Thanks in advance!

  • 0
    TI__Expert 6440 points

    Hi Mikhail,

    ASI loop-backs and pin-to-pin loop-backs serve different purposes. Pin-to-pin loop-backs are to debug board level connectivity issues. It is intended to mimic shorting of the output pin and input pin but in reality it would have small delays resulting from delays of the internal buffers. The ASI loop-backs are done post the decoding of the serial bus data and is more to check if the data is being interpreted correctly. Sample-rate conversions are not done during the ASI loop-back. The data is simply copied from the output register to the input register. The ASIs should operate at the same sampling rate and be clocks should be synchronous for this feature to be used for routing between interfaces.

    Regarding the last question, please note that the ASI loop-backs are not be robust against clock drifts. It is not very clear what the requirement is. Are you looking to convert your PCM data from one clock domain to another? The device also features a DAC to ADC loop-back that loops data at the over-sampled domain between the DAC DSP and the ADC DSP. The smoothing inherent in the interpolation and decimation filters in the DAC and ADC respectively could reduce the effects of noise introduced by clock-jitter. This may be more useful than the ASI loop-backs.

    Best Regards.

  • 0 in reply to Diljith
    Prodigy 20 points

    Hi Diljith,

    It seems I've got all the information I needed.

    Regarding last questions. Yes, I've been looking for a way to convert PCM data from one clock domain to another. And your solution about DAC-to-ADC loopback looks very interesting, I'll try it. But unfortunately I could not find this loopback in the spec at once. Then putting here necessary register for others' reference - (Book 0 / Page 0 / Register 81: ADC Channel Power Control - 0x00 / 0x00 / 0x51 (B0_P0_R81) (bits D2-D5)).

    Thank you for your answer.