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when TLV320ADC3140 is in master mode，how to Configure sampling rates and BCLK to FSYNC frequency ratio？？

TI_st
Prodigy 115 points
Other Parts Discussed in Thread: TLV320ADC3140, TLV320ADC5140, TLV320ADC6140

hi

I am using the TLV320adc3140，I want to configure the TLV320ADC3140  in master mode、 to I2S mode、16K sampling rate、 bclk to FSYNC frequency ratio of 512；

1）Do you have any instruction manual or instruction about the register configuration of this TLV320adc3140/TLV320adc5140/TLV320adc6140?

2） but the FSYNCis always 5.5hz； Please check the code to see if there is a problem with the configuration？The software configuration is as follows：

res=TLV320_Write_Reg(0,0);   //select Bank0
delay_ms(2);

res=TLV320_Write_Reg(0x01,0X01);     // reset
delay_ms(2);


res=TLV320_Write_Reg(0x02,0X81);     //SLEEP_CFG Register ; Internally generated 1.8-V AREG supply , Device is not in sleep mode
delay_ms(2);


res=TLV320_Write_Reg(0x07,0X80);    //ASI_CFG0 Register ; I2S mode, 16 bits, Always transmit 0 for unused cycles
delay_ms(2);


res=TLV320_Write_Reg(0x08,0X20);   //ASI_CFG1 Register; Transmit the LSB for a full cycle ,Bus keeper is always enabled
delay_ms(2);


res=TLV320_Write_Reg(0x13,0XC3);   //MST_CFG0 Register; Device is in master mode, Auto clock configuration is disabled,PLL is enabled,16 MHz
delay_ms(2);


res=TLV320_Write_Reg(0x14,0X1A);   // MST_CFG1 Register; sample rate 16 kHz,BCLK to FSYNC frequency ratio of 512
delay_ms(2);


res=TLV320_Write_Reg(0x73,0XF0);   //IN_CH_EN Register; Channel 1-4 is enabled
delay_ms(2);


res=TLV320_Write_Reg(0x74,0XF0);   //ASI_OUT_CH_EN Register； Channel 1-4 output slot is enabled
delay_ms(2);


res=TLV320_Write_Reg(0x75,0XFF);   //PWR_CFG Register； Power up MICBIAS，Power up all enabled ADC and PDM channels，Power up the PLL
delay_ms(2);


res=TLV320_Write_Reg(0x76,0XF0);   //DEV_STS0 Register；channel 1-4 ADC or PDM channel is powered up
delay_ms(2);


res=TLV320_Write_Reg(0x77,0Xe0);   //DEV_STS1 Register；Device is in active mode with at least one ADC or PDM channel turned on
delay_ms(2);

 

TLV320ADC3140 Configuration code.TXT

 

  • 0
    TI__Expert 6440 points

    Hi,

    Thanks for using ADC3140 in your design.

    Automatic clock configuration is disabled in your configuration. Manual clock configuration is required only for certain combinations of master clock, frame sync, and bit clock.

    Our device has inbuilt support for 16 MHz MCLK with 16 kHz sampling frequency in the master mode and therefore we recommend using auto clock configuration. 

    Therefore, please enable automatic clock configuration i.e. MST_CFG0 Register, AUTO_CLK_CFG = 0, by changing the following register write:

    res=TLV320_Write_Reg(0x13,0XC3);   res=TLV320_Write_Reg(0x13,0x83);

    Best Regards.

     

  • 0 in reply to Diljith
    TI__Expert 6440 points

    Hi,

    In addition to the above there are a few other minor changes.

    1. For I2S mode REG 7 = 0x40

    2. One of the GPIO/GPI's have to be configured as MCLK. The GPIO_CFG0 Register is at page 0x00 register 0x21. The GPI configuration registers are at page 0x00 registers 0x2B and 0x2C.

    Best Regards.

  • 0 in reply to Diljith
    TI__Expert 6440 points

    Hi,

    I shall mark this as resolved. Please reply to this if you need further assistance.

    Best Regards.