TLV320ADC3100: TLV320ADC3100

Hello Rutuja,

Thanks for choosing our device in your design. :)

Can you please send over your schematic again? For some reason I am unable to view it. Based on the register configuration you provided, I assume the following:

1. ASI configured for 32-bit I2S.

2. Only LADC is being used.

3. LADC is powered on and NOT muted

4. IN2L(P) is connected to LPGA

5. LPGA is NOT muted

At first glance, it looks like things are configured correctly. I will have a better understanding once I am able to take a look at the schematic. 

Regards,

Aaron

Hello Aaron,

Thanks for your response.

Schematic :

Regards,

Rutuja

Hello Rutuja,

Thanks for the quick response. One of the first things I noticed is the two voltage dividers for IOVDD and DVDD. We do not recommend this as the load essentially becomes a part of the resistor divider and any changes in that load will change the voltage. We suggest using and LDO for the power supplies. While this may not be the direct cause, it is something to look out for. 

Can you also send over pictures of WCLK, BCLK and DOUT?

Regards,

Aaron

Hello Aaron,

Thank you for your comments, we note that. 

1. BCLK and WCLK

2. bclk, wclk, dout

3. Zoom of the above

Thanks :)

Regards,

Rutuja

Hello Rutuja,

Thanks for the info! I am not seeing anything at DOUT which is odd. Just as a sanity check, have you confirmed that there is in fact a signal on the input?

Regards,

Aaron

Hello Aaron,

We had tested it with a sin wave of 500Hz from the signal generator at the input, the signals look as follows :

At first we thought the problem is with the register configuration. So thought to verify it from you.

Thanks :)

Regards,

Rutuja

Hello Rutuja,

Apologies for the delayed response. 

PGA/ADC blocks look to be powered on and not muted. Can I have a little more information on exactly what inputs are being used? what inputs have you tried to apply input signal at? I can see that you have IN2L selected to be single ended which is fine but you also have other inputs there and I am not sure which input is being used to check DOUT. 

Regards,

Aaron

Dear Aaron,

We only want to use a single input which is IN2L (P) so we provide input at pin 7.

The left PGA and the left ADC are selected rest everything is unselected and muted. 

Also from your previous reply, is there a way to trace input being used to check DOUT 

we selected the DOUT register as : 

7-5 : Reserved

4:  0: DOUT bus keeper enabled

3-1 : 001 DOUT = primary DOUT output for codec interface

0 : DOUT value = 0 when bits 3:1 are programmed to 010 (general purpose output)

I dont know the bit 0 of the DOUT register 53 both options are same, is it a typo?

Thanks and Regards :)

Rutuja

Hello Rutuja,

Register 53 does seems to have an error for Bit D0. I have noted this down for future data sheet revisions. Apologies for any confusion this may have caused. As for next steps, I am currently trying to get a hold of an EVM so I can run the same configuration you provided. In the meantime, can you disable DOUT bus keeper and see if that affects the output?

Regards,

Aaron 

Dear Aaron,

We will wait for your response. meanwhile we will check with the bus keeper disabled.

Thank you. 

Regards,

Rutuja

Dear Aaron,

Do you have a driver for TLV320ADC3100 under raspian OS? can you provide it to us?

Is it much different than the Linux one?

Thanks in advance :)

Regards,

Rutuja

Hello Rutuja,

We unfortunately do not offer any driver for the ADC3101. You can find a Linux Driver for this device here. As for what you are looking for, there may be one available somewhere online. 

Regards,

Aaron

Dear Aaron,

Thank you for your response.

We still await your comments on the register configuration.

Please let us know if they are configured correctly or we still need to make any changes.

Best Regards :)

Rutuja Salvi

Hello Rutuja,

I really appreciate your patience. Don't worry, I have not forgotten. :)

I have attached a .txt file that has some EVM GUI code. Can you please use this as an example to get data out of the LADC? The format of the commands are :

w 30 xx yy 

where

w = write

30 = address

xx = register in hex

yy = value in hex

Let me know if this works. I was able to confirm this works on an EVM. One thing to note, that even with no data, there should be some small noise on DOUT. This makes me think that somehow the ADC getting muted or powered down somehow.

Regards,

Aaron 

Dear Aaron,

Thank you for your response :)

I cannot find the .txt file, can you please resend it?

Regards,

Rutuja

Rutuja,

Not sure why it did not go through. Let me know if you receive it now. Please ignore the CLK generation. This was configured for an Fs of 44.1kHz using the generated CLK on the EVM. 

Please start out with this basic configuration that should be a good indicator if the issue is a configuration issue. 

Regards,

Aaron

###############################################
# Software Reset
###############################################
#
# Select Page 0
w 30 00 00
#
# Initialize the device through software reset
w 30 01 01
###############################################

###############################################
# Clock Settings
# ---------------------------------------------
# The codec receives: MCLK = 11.2896 MHz,
# BCLK = 2.8224 MHz, WCLK = 44.1 kHz
###############################################
#
# Select Page 0
w 30 00 00
#
# NADC = 1, MADC = 2
w 30 12 81 82
#
# AOSR = 128 (default)
#
###############################################

###############################################
# Audio Settings 
###############################################
#
# Default Setting: I2S, 16-bits, Slave Mode (BCLK and WCLK are inputs), 3-stating of DOUT disabled
w 30 1b 31

###############################################
# Signal Processing Settings
###############################################
#
# Select Page 0
w 30 00 00
#
# Set the ADC Mode to PRB_P1 (default)
w 30 3d 01
#
###############################################

###############################################
# Recording Setup
###############################################
#
# Left ADC Vol = 0dB
w 30 53 00
#
# Select Page 1
w 30 00 01
#
# Mic Bias Powered Down
w 30 33 00
#
# Left ADC Input selection for Left PGA = IN1L(P) as Single-Ended
w 30 34 f3
#
# Left Analog PGA Seeting = 0dB
w 30 3b 00
#
# Select Page 0
w 30 00 00
#
# Power-up Left ADC
w 30 51 80
#
# Unmute Left(Gain = 0dB)
w 30 52 08

Hello Aaron,

Thank you, we received it. :)

We will inform you about the status by tomorrow. 

From your previous posts :

It does not work with bus keeper disabled.

Regards,

Rutuja

Dear Aaron,

We tried with the program you shared with us, with the clock configuration of our own and the address 0x18.

On the input pin we provide a (2Vpp : 0.707Vrms)

It did not record anything.

But when we run the recording script, we see some noise on the DOUT pin on the oscilloscope.

On the digital oscilloscope it is just a flat line. which means it outputs only 0. 

We also checked the register values after the recording was done and notice that the registers retain their values. 

Regards,

Rutuja

Hello Rutuja,

Can we take this offline through email? I can send you a friend request and we can go from there.

Regards,

Aaron

Dear Aaron,

Thank you for your response.

Sure we can do that offline through email.

Do I need to share my email id here? or you can send me request on the registered email?  

Regards,

Rutuja

Hello Rutuja,

I can send a an email through the one you registered with if this is okay. No need to post publicly. 

Regards,

Aaron

Hello Aaron,

You can contact me on the registered email.

Regards,

Rutuja

Hi Rutuja,

Thanks. I send an email to you. I will close the thread as we will continue this offline.

Regards,

Aaron