• State
  • Locked Locked
  • Replies 23 replies
  • Subscribers 29 subscribers
  • Views 716 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLV320ADC3100: TLV320ADC3100

Rutuja Salvi
Prodigy 210 points
Part Number: TLV320ADC3100

Hello,

I wanted to use this ADC in our project, I have designed a PCB for the same and also configured registers with the help of a raspberry pi(master). but the ADC did not record any signal. It would be nice if we get some help troubleshooting the circuit or the register configuration.

1. Schematic

 2. Power Supply and Connections

AVDD : 3.3V

AVSS : GND

DVDD : 1.8V 

DVSS : GND

IOVDD : 1.8V

Pull up resistors for SDA and SCL : 1.6KΩ

3. Initial Start up

After connecting all the power supplies, the RESET pin is held low for 1s. 

checking the I2C address :

3. Register Configuration :

i) page selection : page 0

Page Register No. Name Register Bits Binary Values Decimal Values
7 6 5 4 3 2 1 0
0 1 Software Reset Field Descriptions 0 0 0 0 0 0 0 1 00000001 1
0 4 Clock-Gen Multiplexing 0 0 0 0 0 1 1 1 00000111 7
0 5 PLL P and R-VAL 1 0 0 1 0 0 0 1 10010001 145
0 6 PLL J-VAL Field Descriptions 0 0 0 0 0 1 0 0 00000100 4
0 7 PLL D-VAL MSB 0 0 0 0 0 0 0 0 00000000 0
0 8 PLL D-VAL LSB 0 0 0 0 0 0 0 0 00000000 0
0 18 ADC NADC Clock Divide 1 0 0 0 0 0 0 1 10000001 129
0 19 ADC MADC Clock Divide 1 0 0 0 0 1 0 0 10000100 132
0 20 ADC AOSR Field Descriptions 0 1 0 0 0 0 0 0 01000000 64
0 21 ADC IADC Field Descriptions 1 0 1 1 1 1 0 0 10111100 188
0 27 ADC Audio Interface Control 1 Field Descriptions 0 0 1 1 0 0 0 1 00110001 49
0 38 I2S TDM Control Register Field Descriptions 0 0 0 0 0 1 1 0 00000110 6
0 53 DOUT (OUT Pin) Control Field Descriptions 0 0 0 0 0 0 1 0 00000010 2
0 61 ADC Processing Block Selection Field Descriptions 0 0 0 0 0 0 0 1 00000001 1

ii) page selection : page 1

Page Register No. Name Register Bits Binary Values Decimal Values
7 6 5 4 3 2 1 0
1 51 MICBIAS Control Field Descriptions 0 0 0 0 0 0 0 0 00000000 0
1 52 Left ADC Input Selection for Left PGA 1 1 1 1 0 0 1 1 11110011 243
1 54 Left ADC Input Selection for Left PGA Field Description 0 0 1 1 1 1 1 1 00111111 63
1 55 Right ADC Input Selection for Right PGA Field Descriptions 1 1 1 1 1 1 1 1 11111111 255
1 57 Right ADC Input Selection for Right PGA Field Description 0 0 1 1 1 1 1 1 00111111 63
1 59 Left Analog PGA Settings Field Descriptions 0 0 0 0 0 0 0 0 00000000 0
1 60 Right Analog PGA Settings Field Descriptions 1 0 0 0 0 0 0 0 10000000 128
1 62 ADC Analog PGA Flags 0 0 0 0 0 0 1 0 00000010 2

iii) page selection : page 0

Page Register No. Name Register Bits Binary Values Decimal Values
7 6 5 4 3 2 1 0
0 81 ADC Digital Field Descriptions 1 0 0 0 0 0 0 1 10000001 129
0 82 ADC Fine Volume Control Field Descriptions 0 0 0 0 1 0 0 0 00001000 8
0 83 Left ADC Volume Control Field Descriptions 0 1 0 0 0 0 0 0 01000000 64
0 84 Right ADC Volume Control Field Descriptions 0 1 0 0 0 0 0 0 01000000 64
0 86 Left AGC Control 1 Field Descriptions 1 0 0 0 0 0 0 0 10000000 128
0 93 Left AGC Gain Applied Field Descriptions 0 0 0 0 0 0 0 0 00000000 0
0 94 Right AGC Control 1 Field Descriptions 0 0 0 0 0 0 0 0 00000000 0
0 101 Right AGC Gain Applied Field Descriptions 0 0 0 0 0 0 0 0 00000000 0

4. Clock Settings :

PLL_CLK = BCLK = 2.8224 Mhz, P =1 , R = 1, J = 4, D = 0000, NADC = 1, MADC = 4, AOSR = 64, ADC_FS = 44100

I am able to read from and write to the registers, however I am not getting anything at the DOUT if i try recording an audio with I2S. It would be nice, if we receive some comments and tips to resolve this issue. Many thanks in advance :)

Rutuja :)

  • 0
    TI__Mastermind 22950 points

    Hello Rutuja,

    Thanks for choosing our device in your design. :)

    Can you please send over your schematic again? For some reason I am unable to view it. Based on the register configuration you provided, I assume the following:

    1. ASI configured for 32-bit I2S.

    2. Only LADC is being used.

    3. LADC is powered on and NOT muted

    4. IN2L(P) is connected to LPGA

    5. LPGA is NOT muted

    At first glance, it looks like things are configured correctly. I will have a better understanding once I am able to take a look at the schematic. 

    Regards,

    Aaron

  • 0 in reply to Aaron Estrada
    Prodigy 210 points

    Hello Aaron,

    Thanks for your response.

    Schematic :

    Regards,

    Rutuja

  • 0 in reply to Rutuja Salvi
    TI__Mastermind 22950 points

    Hello Rutuja,

    Thanks for the quick response. One of the first things I noticed is the two voltage dividers for IOVDD and DVDD. We do not recommend this as the load essentially becomes a part of the resistor divider and any changes in that load will change the voltage. We suggest using and LDO for the power supplies. While this may not be the direct cause, it is something to look out for. 

    Can you also send over pictures of WCLK, BCLK and DOUT?

    Regards,

    Aaron

  • 0 in reply to Aaron Estrada
    Prodigy 210 points

    Hello Aaron,

    Thank you for your comments, we note that. 

    1. BCLK and WCLK

    2. bclk, wclk, dout

    3. Zoom of the above

    Thanks :)

    Regards,

    Rutuja

  • 0 in reply to Rutuja Salvi
    TI__Mastermind 22950 points

    Hello Rutuja,

    Thanks for the info! I am not seeing anything at DOUT which is odd. Just as a sanity check, have you confirmed that there is in fact a signal on the input?

    Regards,

    Aaron

  • 0 in reply to Aaron Estrada
    Prodigy 210 points

    Hello Aaron,

    We had tested it with a sin wave of 500Hz from the signal generator at the input, the signals look as follows :

    At first we thought the problem is with the register configuration. So thought to verify it from you.

    Thanks :)

    Regards,

    Rutuja

  • 0 in reply to Rutuja Salvi
    TI__Mastermind 22950 points

    Hello Rutuja,

    Apologies for the delayed response. 

    PGA/ADC blocks look to be powered on and not muted. Can I have a little more information on exactly what inputs are being used? what inputs have you tried to apply input signal at? I can see that you have IN2L selected to be single ended which is fine but you also have other inputs there and I am not sure which input is being used to check DOUT. 

    Regards,

    Aaron

  • 0 in reply to Aaron Estrada
    Prodigy 210 points

    Dear Aaron,

    We only want to use a single input which is IN2L (P) so we provide input at pin 7.

    The left PGA and the left ADC are selected rest everything is unselected and muted. 

    Also from your previous reply, is there a way to trace input being used to check DOUT 

    we selected the DOUT register as : 

    7-5 : Reserved

    4:  0: DOUT bus keeper enabled

    3-1 : 001 DOUT = primary DOUT output for codec interface

    0 : DOUT value = 0 when bits 3:1 are programmed to 010 (general purpose output)

    I dont know the bit 0 of the DOUT register 53 both options are same, is it a typo?

    Thanks and Regards :)

    Rutuja

  • 0 in reply to Rutuja Salvi
    TI__Mastermind 22950 points

    Hello Rutuja,

    Register 53 does seems to have an error for Bit D0. I have noted this down for future data sheet revisions. Apologies for any confusion this may have caused. As for next steps, I am currently trying to get a hold of an EVM so I can run the same configuration you provided. In the meantime, can you disable DOUT bus keeper and see if that affects the output?

    Regards,

    Aaron 

  • 0 in reply to Aaron Estrada
    Prodigy 210 points

    Dear Aaron,

    We will wait for your response. meanwhile we will check with the bus keeper disabled.

    Thank you. 

    Regards,

    Rutuja

  • 0 in reply to Aaron Estrada
    Prodigy 210 points

    Dear Aaron,

    Do you have a driver for TLV320ADC3100 under raspian OS? can you provide it to us?

    Is it much different than the Linux one?

    Thanks in advance :)

    Regards,

    Rutuja

  • 0 in reply to Rutuja Salvi
    TI__Mastermind 22950 points

    Hello Rutuja,

    We unfortunately do not offer any driver for the ADC3101. You can find a Linux Driver for this device here. As for what you are looking for, there may be one available somewhere online. 

    Regards,

    Aaron

  • 0 in reply to Aaron Estrada
    Prodigy 210 points

    Dear Aaron,

    Thank you for your response.

    We still await your comments on the register configuration.

    Please let us know if they are configured correctly or we still need to make any changes.

    Best Regards :)

    Rutuja Salvi

  • 0 in reply to Rutuja Salvi
    TI__Mastermind 22950 points

    Hello Rutuja,

    I really appreciate your patience. Don't worry, I have not forgotten. :)

    I have attached a .txt file that has some EVM GUI code. Can you please use this as an example to get data out of the LADC? The format of the commands are :

    w 30 xx yy 

    where

    w = write

    30 = address

    xx = register in hex

    yy = value in hex

    Let me know if this works. I was able to confirm this works on an EVM. One thing to note, that even with no data, there should be some small noise on DOUT. This makes me think that somehow the ADC getting muted or powered down somehow.

    Regards,

    Aaron 

  • 0 in reply to Aaron Estrada
    Prodigy 210 points

    Dear Aaron,

    Thank you for your response :)

    I cannot find the .txt file, can you please resend it?

    Regards,

    Rutuja

  • 0 in reply to Rutuja Salvi
    TI__Mastermind 22950 points

    Rutuja,

    Not sure why it did not go through. Let me know if you receive it now. Please ignore the CLK generation. This was configured for an Fs of 44.1kHz using the generated CLK on the EVM. 

    Please start out with this basic configuration that should be a good indicator if the issue is a configuration issue. 

    Regards,

    Aaron

    ADC3100_LADC.txt
    Fullscreen
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16
    17
    18
    19
    20
    21
    22
    23
    24
    25
    26
    27
    28
    29
    30
    31
    32
    33
    34
    35
    36
    37
    38
    39
    40
    41
    42
    43
    44
    45
    46
    47
    48
    49
    50
    51
    52
    53
    54
    55
    56
    57
    58
    59
    60
    61
    62
    63
    64
    65
    66
    67
    ###############################################
    # Software Reset
    ###############################################
    #
    # Select Page 0
    w 30 00 00
    #
    # Initialize the device through software reset
    w 30 01 01
    ###############################################
    ###############################################
    # Clock Settings
    # ---------------------------------------------
    # The codec receives: MCLK = 11.2896 MHz,
    # BCLK = 2.8224 MHz, WCLK = 44.1 kHz
    ###############################################
    #
    # Select Page 0
    w 30 00 00
    #
    # NADC = 1, MADC = 2
    w 30 12 81 82
    #
    # AOSR = 128 (default)
    #
    ###############################################
    ###############################################
    # Audio Settings
    ###############################################
    #
    # Default Setting: I2S, 16-bits, Slave Mode (BCLK and WCLK are inputs), 3-stating of DOUT disabled
    w 30 1b 31
    ###############################################
    # Signal Processing Settings
    ###############################################
    #
    # Select Page 0
    w 30 00 00
    #
    # Set the ADC Mode to PRB_P1 (default)
    w 30 3d 01
    #
    ###############################################
    ###############################################
    # Recording Setup
    ###############################################
    #
    # Left ADC Vol = 0dB
    w 30 53 00
    #
    # Select Page 1
    w 30 00 01
    #
    # Mic Bias Powered Down
    w 30 33 00
    #
    # Left ADC Input selection for Left PGA = IN1L(P) as Single-Ended
    w 30 34 f3
    #
    # Left Analog PGA Seeting = 0dB
    w 30 3b 00
    #
    # Select Page 0
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0 in reply to Aaron Estrada
    Prodigy 210 points

    Hello Aaron,

     

    Thank you, we received it. :)

    We will inform you about the status by tomorrow. 

     

    From your previous posts :

    It does not work with bus keeper disabled.

     

    Regards,

    Rutuja

  • 0 in reply to Aaron Estrada
    Prodigy 210 points

    Dear Aaron,

    We tried with the program you shared with us, with the clock configuration of our own and the address 0x18.

    On the input pin we provide a (2Vpp : 0.707Vrms)

    It did not record anything.

    But when we run the recording script, we see some noise on the DOUT pin on the oscilloscope.

    On the digital oscilloscope it is just a flat line. which means it outputs only 0. 

    We also checked the register values after the recording was done and notice that the registers retain their values. 

    Regards,

    Rutuja

  • 0 in reply to Rutuja Salvi
    TI__Mastermind 22950 points

    Hello Rutuja,

    Can we take this offline through email? I can send you a friend request and we can go from there.

    Regards,

    Aaron

  • 0 in reply to Aaron Estrada
    Prodigy 210 points

    Dear Aaron,

    Thank you for your response.

    Sure we can do that offline through email.

    Do I need to share my email id here? or you can send me request on the registered email?  

    Regards,

    Rutuja

  • 0 in reply to Rutuja Salvi
    TI__Mastermind 22950 points

    Hello Rutuja,

    I can send a an email through the one you registered with if this is okay. No need to post publicly. 

    Regards,

    Aaron

  • 0 in reply to Aaron Estrada
    Prodigy 210 points

    Hello Aaron,

    You can contact me on the registered email.

    Regards,

    Rutuja

  • 0 in reply to Rutuja Salvi
    TI__Mastermind 22950 points

    Hi Rutuja,

    Thanks. I send an email to you. I will close the thread as we will continue this offline.

    Regards,

    Aaron