TLV320AIC3268: I2S signal WCLK equal to LRCLK?

Hello,

Good question.  Yes, WCLK (Word Clock) is another name for the LRCLK (Left/Right Clock) signal in an Audio Serial Interface (ASI) bus.

Here's a few comments on the schematic:

1.) the input divider is likely included to prevent saturation of signals up to the full-scale input level of the ADC to account for some inherent ADC gain error.  The values could be reduced by a factor of 2-5x to help reduce their noise contributions without changing the performance too much.

2.)  It looks like the DOUT1 pin is not connected and the processor will not directly read the ADC outputs.

3.)  "SAI3_FS" is the correct signal to connect to the WCLK input.

4.)  SAI3_TXC should be verified to be the correct BCLK signal.  This needs to be the correct multiple of WCLK (128/256/512, etc) with correct edge timings.