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Original question:

TAS3251: TAS3251 I2S Input (As Slave) Not Working

TAS3251: EVMboard I2S Input (As Slave) Not Working

user5257410
Prodigy 140 points
Part Number: TAS3251

Hi,

My TAS3251EVM is not working. The configuration I set for the TAS3251EVM is as below:

  1. TAS3251EVM as slave device (I2S)
  2. The I2S master is from my prototype board - providing the BCLK, SDIN and LRCK to the TAS3251EVM
  3. R54 and R55 is removed (I2C from MSP430), supplying I2C from my prototype board.
  4. J37 - OUT (AIB I2S)
  5. J35 - Slave enable
  6. PLL is enabled.
  7. R168 is removed, and /I2S-BUF-EN is forced to be low (connect to GND).

At the test pin between the heat sink and J9, I can see that the data of BCLK, LRCLK and SDIN are correct.

I can see that a 600kHz switching waveform was output from the SPK_OUT pin (but no sound).

PLL is configured as below.

please advise me.

  • 0
    TI__Mastermind 19080 points

    Hi,

    As TAS3251 has a DSP module inside, you need to do some initialization. Have you got the PPC3 GUI?

    Regards,

    Sam

  • 0 in reply to Sam(MPAA) Zhang
    Prodigy 140 points

    Hi,

    Thank you for your reply.

    Yes, I use PPC3 GUI and TAS3251-SW (and using the header file from TAS3251-SW).

    I wonder if there is something wrong with the order of register tuning.

    A part of the header file (register tuning part) is posted here.

    //register tuning
    { 0x00, 0x00 },
    { 0x7f, 0x00 },
    { 0x00, 0x00 },

    //SDOUT control

    { 0x07, 0x00 }, //De-emphasis disable, SDOUT is the DSP output

    { 0x08, 0x20 }, //SDOUT is output, mute control disable (PCM to TPA)
    { 0x55, 0x00 }, //SD output selection off

    //PLL control
    { 0x09, 0x00 }, //I2S slave mode
    { 0x0c, 0x00 }, //master mode MCLK divider disable

    { 0x25, 0x7f }, //clock detection ignore, disable clock divider auto set

    { 0x04, 0x01 }, //PLL enable

    { 0x0d, 0x11 }, //PLL source is SCLK, DSP clock source is PLL clock
    { 0x0e, 0x12 }, //DAC clock source is PLL, OSR clock is PLL
    { 0x0f, 0x02 }, //NCP clock source is PLL
    { 0x14, 0x00 }, //PLL factor P = 1
    { 0x15, 0x10 }, //PLL factor J = 16
    { 0x16, 0x00 }, //PLL factor D1 = 0
    { 0x17, 0x00 }, //PLL factor D2 = 0
    { 0x18, 0x01 }, //PLL factor R = 2
    { 0x1b, 0x01 }, //DSP clock divide by 2
    { 0x1c, 0x0F }, //DAC clock divide by 16
    { 0x1d, 0x03 }, //NCP clock divide by 4
    { 0x1e, 0x07 }, //OSR clock divide by 8

    //DSP reset release, standby mode request off
    { 0x02, 0x00 },

    //Digital volume control
    { 0x00, 0x00 },
    { 0x7f, 0x00 },
    { 0x00, 0x00 },
    { 0x3d, 0x30 },
    { 0x3e, 0x30 },

    //manually tuning data so far
    { 0x00, 0x00 },
    { 0x7f, 0x00 },
    { 0x00, 0x01 }, //move to page 1
    { 0x02, 0x00 }, //analog gain = 0dB
    { 0x00, 0x00 }, 
    { 0x7f, 0x00 },
    { 0x03, 0x00 }, //unmute device
    { 0x2a, 0x11 },

    sorry for the long sentence.

    please advise me.

    Best regards.

  • 0 in reply to user5257410
    Prodigy 140 points

    I managed to solve it myself.

    After all, there was an error in register tuning.

    Of the Dump files used to play the TAS5766, I copied and pasted the data of page0 and page1 and added the data for setting the book (0x00, 0x00, 0x7f, 0x00), and a sound came out.

    The registration setting data is posted below.

    // Page 0 (0x00) Dump
    { 0x00, 0x00 },
    { 0x7f, 0x00 },
    { 0x00, 0x00 },
    { CFG_META_BURST, 126 },
    { 0x83, 0x00 },
    // reg.add : 0x04, 0x05 0x04:PLL Enable=0x01
    { 0x01, 0x01 },
    // reg.add : 0x06, 0x07
    { 0x00, 0x00 },
    // reg.add : 0x08, 0x09 0x08:Mutecontrol/GPIO Output enable = 0x3c
    { 0x10, 0x00 },
    // reg.add : 0x0a, 0x0b
    { 0x00, 0x01 },
    // reg.add : 0x0c, 0x0d 0x0d:PLL reference Clock b4=1:BCK
    { 0x7c, 0x11 },
    // reg.add : 0x0e, 0x0f
    { 0x00, 0x00 },
    // reg.add : 0x10, 0x11
    { 0x00, 0x00 },
    // reg.add : 0x12, 0x13
    { 0x00, 0x10 },
    // reg.add : 0x14, 0x15 0x14:PLL P 0, 0x15:PLL J 16(0x10)
    { 0x00, 0x10 },
    // reg.add : 0x16, 0x17 0x16:PLL D 0, 0x17:PLL D 0
    { 0x00, 0x00 },
    // reg.add : 0x18, 0x19 0x18:PLL R 2(0001)
    // PLL = R*J.D/P*REF CLK(MHz)
    { 0x01, 0x01 },
    // reg.add : 0x1a, 0x1b 0x1b:DSP clock divide 2(0001)
    { 0x80, 0x01 },
    // reg.add : 0x1c, 0x1d 0x1c:DAC clock divide 16(1111), 0x1d:NCP clock divider 4(0011)
    { 0x0f, 0x03 },
    // reg.add : 0x1e, 0x1f 0x1e:OSR clock divide 8(0111)
    { 0x07, 0x04 },
    // reg.add : 0x20, 0x21
    { 0x00, 0x00 },
    // reg.add : 0x22, 0x23 0x23:IDAC(MSB)DSP clock cycle for audio 1frame 0x04
    { 0x00, 0x04 },
    // reg.add : 0x24, 0x25 0x24:IDAC(LSB)DSP clock cyccle for audio 1frame 0x00
    // IDAC = 0x0400 (1024)
    // 0x25 b1:disable clock autoset b4:ignore clock halt detection
    { 0x00, 0x1a },
    // reg.add : 0x26, 0x27
    { 0xf3, 0x04 },
    // reg.add : 0x28, 0x29
    { 0x02, 0x00 },
    // reg.add : 0x2a, 0x2b
    { 0x11, 0x1f },
    // reg.add : 0x2c, 0x2d
    { 0x07, 0x00 },
    // reg.add : 0x2e, 0x2f
    { 0x00, 0x00 },
    // reg.add : 0x30, 0x31
    { 0x00, 0x00 },
    // reg.add : 0x32, 0x33
    { 0x00, 0x00 },
    // reg.add : 0x34, 0x35
    { 0x00, 0x00 },
    // reg.add : 0x36, 0x37
    { 0x00, 0x00 },
    // reg.add : 0x38, 0x39
    { 0x00, 0x00 },
    // reg.add : 0x3a, 0x3b
    { 0x00, 0x77 },
    // reg.add : 0x3c, 0x3d
    { 0x00, 0x1d },
    // reg.add : 0x3e, 0x3f
    { 0x1d, 0x22 },
    // reg.add : 0x40, 0x41
    { 0x02, 0x04 },
    // reg.add : 0x42, 0x43
    { 0x14, 0x05 },
    // reg.add : 0x44, 0x45
    { 0x00, 0x00 },
    // reg.add : 0x46, 0x47
    { 0x00, 0x00 },
    // reg.add : 0x48, 0x49
    { 0x55, 0x00 },
    // reg.add : 0x4a, 0x4b
    { 0x00, 0x00 },
    // reg.add : 0x4c, 0x4d
    { 0x00, 0x00 },
    // reg.add : 0x4e, 0x4f
    { 0x00, 0x00 },
    // reg.add : 0x50, 0x51
    { 0x00, 0x00 },
    // reg.add : 0x52, 0x53
    { 0x00, 0x00 },
    // reg.add : 0x54, 0x55
    { 0x00, 0x00 },
    // reg.add : 0x56, 0x57
    { 0x00, 0x00 },
    // reg.add : 0x58, 0x59
    { 0x81, 0x00 },
    // reg.add : 0x5a, 0x5b
    { 0x00, 0x36 },
    // reg.add : 0x5c, 0x5d
    { 0x00, 0x40 },
    // reg.add : 0x5e, 0x5f
    { 0x00, 0x00 },
    // reg.add : 0x60, 0x61
    { 0x01, 0x10 },
    // reg.add : 0x62, 0x63
    { 0x00, 0x00 },
    // reg.add : 0x64, 0x65
    { 0x00, 0x01 },
    // reg.add : 0x66, 0x67
    { 0x0f, 0x03 },
    // reg.add : 0x68, 0x69
    { 0x07, 0x10 },
    // reg.add : 0x6a, 0x6b
    { 0xd0, 0x10 },
    // reg.add : 0x6c, 0x6d
    { 0x00, 0x00 },
    // reg.add : 0x6e, 0x6f
    { 0x01, 0x08 },
    // reg.add : 0x70, 0x71
    { 0x00, 0x83 },
    // reg.add : 0x72, 0x73
    { 0x03, 0x00 },
    // reg.add : 0x74, 0x75
    { 0x04, 0x00 },
    // reg.add : 0x76, 0x77
    { 0x88, 0x01 },
    // reg.add : 0x78, 0x79
    { 0x00, 0x00 },
    // reg.add : 0x7a, 0x7b
    { 0x00, 0x00 },
    // reg.add : 0x7c, 0x7d
    { 0x00, 0x00 },
    // reg.add : 0x7e, 0x7f
    { 0x00, 0x00 },

    // Page 1 (0x01) Dump
    { 0x00, 0x00 },
    { 0x7f, 0x00 },
    { 0x00, 0x01 },
    { CFG_META_BURST, 128 },
    { 0x81, 0x00 },
    // reg.add : 0x02, 0x03 0x02:Analog Gain 0:0dB
    { 0x00, 0x00 },
    // reg.add : 0x04, 0x05
    { 0x03, 0x01 },
    // reg.add : 0x06, 0x07
    { 0x01, 0x00 },
    // reg.add : 0x08, 0x09
    { 0x10, 0x01 },
    // reg.add : 0x0a, 0x0b
    { 0x33, 0x11 },
    // reg.add : 0x0c, 0x0d
    { 0x11, 0x11 },
    // reg.add : 0x0e, 0x0f
    { 0x00, 0x01 },
    // reg.add : 0x10, 0x11
    { 0x00, 0x00 },
    // reg.add : 0x12, 0x13
    { 0x00, 0x00 },
    // reg.add : 0x14, 0x15
    { 0x00, 0x00 },
    // reg.add : 0x16, 0x17
    { 0x00, 0x00 },
    // reg.add : 0x18, 0x19
    { 0x00, 0x00 },
    // reg.add : 0x1a, 0x1b
    { 0x00, 0x00 },
    // reg.add : 0x1c, 0x1d
    { 0x00, 0x00 },
    // reg.add : 0x1e, 0x1f
    { 0x00, 0x00 },
    // reg.add : 0x20, 0x21
    { 0x00, 0x00 },
    // reg.add : 0x22, 0x23
    { 0x00, 0x00 },
    // reg.add : 0x24, 0x25
    { 0x00, 0x00 },
    // reg.add : 0x26, 0x27
    { 0x00, 0x00 },
    // reg.add : 0x28, 0x29
    { 0x00, 0x00 },
    // reg.add : 0x2a, 0x2b
    { 0x00, 0x00 },
    // reg.add : 0x2c, 0x2d
    { 0x00, 0x00 },
    // reg.add : 0x2e, 0x2f
    { 0x00, 0x00 },
    // reg.add : 0x30, 0x31
    { 0x00, 0x00 },
    // reg.add : 0x32, 0x33
    { 0x00, 0x00 },
    // reg.add : 0x34, 0x35
    { 0x00, 0x00 },
    // reg.add : 0x36, 0x37
    { 0x00, 0x00 },
    // reg.add : 0x38, 0x39
    { 0x00, 0x00 },
    // reg.add : 0x3a, 0x3b
    { 0x00, 0x00 },
    // reg.add : 0x3c, 0x3d
    { 0x00, 0x00 },
    // reg.add : 0x3e, 0x3f
    { 0x00, 0x00 },
    // reg.add : 0x40, 0x41
    { 0x00, 0x00 },
    // reg.add : 0x42, 0x43
    { 0x00, 0x00 },
    // reg.add : 0x44, 0x45
    { 0x00, 0x00 },
    // reg.add : 0x46, 0x47
    { 0x00, 0x00 },
    // reg.add : 0x48, 0x49
    { 0x00, 0x00 },
    // reg.add : 0x4a, 0x4b
    { 0x00, 0x00 },
    // reg.add : 0x4c, 0x4d
    { 0x00, 0x00 },
    // reg.add : 0x4e, 0x4f
    { 0x00, 0x00 },
    // reg.add : 0x50, 0x51
    { 0x00, 0x00 },
    // reg.add : 0x52, 0x53
    { 0x00, 0x00 },
    // reg.add : 0x54, 0x55
    { 0x00, 0x00 },
    // reg.add : 0x56, 0x57
    { 0x00, 0x00 },
    // reg.add : 0x58, 0x59
    { 0x00, 0x00 },
    // reg.add : 0x5a, 0x5b
    { 0x00, 0x00 },
    // reg.add : 0x5c, 0x5d
    { 0x00, 0x00 },
    // reg.add : 0x5e, 0x5f
    { 0x00, 0x00 },
    // reg.add : 0x60, 0x61
    { 0x00, 0x00 },
    // reg.add : 0x62, 0x63
    { 0x00, 0x00 },
    // reg.add : 0x64, 0x65
    { 0x00, 0x00 },
    // reg.add : 0x66, 0x67
    { 0x00, 0x00 },
    // reg.add : 0x68, 0x69
    { 0x00, 0x00 },
    // reg.add : 0x6a, 0x6b
    { 0x00, 0x00 },
    // reg.add : 0x6c, 0x6d
    { 0x00, 0x00 },
    // reg.add : 0x6e, 0x6f
    { 0x00, 0x00 },
    // reg.add : 0x70, 0x71
    { 0x00, 0x00 },
    // reg.add : 0x72, 0x73
    { 0x00, 0x00 },
    // reg.add : 0x74, 0x75
    { 0x00, 0x00 },
    // reg.add : 0x76, 0x77
    { 0x00, 0x00 },
    // reg.add : 0x78, 0x79
    { 0x00, 0x00 },
    // reg.add : 0x7a, 0x7b
    { 0x00, 0x00 },
    // reg.add : 0x7c, 0x7d
    { 0x00, 0x00 },
    // reg.add : 0x7e, 0x7f
    { 0x00, 0x00 },

    };

    I think it is desirable to set it in auto increment mode without omission.

    Thanks.

  • 0 in reply to user5257410
    Prodigy 10 points

    hi

    how find these registers description?i can't find them in TAS3251 .PDF

  • 0 in reply to user3981177
    Prodigy 140 points

    hi

    I can't find them on the datasheet as well.

    I guess that the register that is not written in the data sheet may be set to the same data as the reset state.

    (Or, even if it is set, it may not be written.)

    All register information at the reset state should be visible from PPC3.

  • 0 in reply to user5257410
    TI__Mastermind 19080 points

    Hi,

    Some DSP tuning related registers are described in the "TAS3251 Process Flow".

    http://www.ti.com/lit/an/slaa799a/slaa799a.pdf?&ts=1589177376817