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Original question:

SRC4392: Confusing description of PLL2 operation.

SRC4392: DIR Continuous Sample Rate Frequency?

David Kroeger
Prodigy 20 points

Part Number: SRC4392

Does the DIR output provide the full 20KHz to 192 KHz sample rate range without having to change any registers?  My system seems to need to change the PLL2 output frequency divide by number to produce the correct LR clock once I go above 48 KHz.

  • 0
    Genius 3945 points

    It should not require any register changes.

    I have an SRC4392-based design that works over the 32 kHz to 192 kHz range with no intervention required.

    Make sure your registers are set correctly. I had an issue in board bring-up that baffled me for a bit -- the DIR would synchronize on 48 kHz and multiple inputs but not 44.1 kHz and its multiples. One of the registers being loaded was wrong.

  • 0 in reply to Andy Peters
    Intellectual 470 points

    Yes and no...

    I just had this problem with a sample rate of 200kHz.

    Setup:

    SPDIF input rate: 200kHz

    I2S (Port A) output rates: 48, 50, 96, 100, 192 or 200kHz

    So the SRC PLL1 registers 1..3 need to be set to 25.6MHz for I2S output rate of 200kHz.

    For all other sampling rates the setting to 24.576MHz (for 192kHz) was good enough.

    Here in the support forum I was told that one setting would be enough. No, it is not.

    Documentation is really a little too sparse or even lacking important information in the datasheet.

  • 0 in reply to Christian Erle
    Genius 3945 points

    Christian Erle55 said:

    Yes and no...

    I just had this problem with a sample rate of 200kHz.

    Setup:

    SPDIF input rate: 200kHz

    I2S (Port A) output rates: 48, 50, 96, 100, 192 or 200kHz

    So the SRC PLL1 registers 1..3 need to be set to 25.6MHz for I2S output rate of 200kHz.

    For all other sampling rates the setting to 24.576MHz (for 192kHz) was good enough.

    For the moment it looks like you only want to take a S/PDIF input and generate I2S on one of the audio serial ports, no SRC involved. The recovered modulator clock is then on RXCKO, and that clock also has to be selected as the master clock source for the audio serial port.

    Remember that the PLL1 uses a reference clock to synthesize the clock that oversamples the receive input. The register values D, J and P must be set to the value for that reference clock, not to the MCLK you expect to be recovered from the input data. So -- what is your reference clock frequency? See the description of registers 0x0F, 0x10 and 0x11 for the discussion on how to derive D, J and P values for your reference clock frequency.

    And is the reference clock select register set correctly? 

    In other words, the PLL1 configuration is set based on the reference clock, which is generally fixed, and not based on the frequency of the audio data coming in over S/PDIF which can change.

    Yeah, the documentation is not exactly clear on this.

    NB: I don't have any source capable of generating audio data at frequencies other than the standards so I can't test the above.