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Original question:

SRC4192: RCKI

SRC4192: /RDY flag

Mochi
Genius 4285 points

Part Number: SRC4192

Hello,

On our customer evaluation, SRC4192 /RDY pin function is little bit strange.

/RDY comes to L when clocking LRCKI and BCKI.

/RDY keeping L when stop LRCKI and clocking BCKI.

/RDY comes to H when stop LRCKI and BCKI

.

We expected Fs estimator is monitoring the ratio of LRCKI and LRCKO, it should not BCKI and BCKO.

Do you see any issue in their evaluation configuration?

I know one concern that RCKI rate is 24MHz, so it is not audio clock.

Is that root cause of this phenomena?

 

Regards,

Mochizuki

SRC4192 RDY.pptx

  • 0
    TI__Mastermind 23050 points

    Hi Mochizuki,

    The respective ratios of BCLK/FSYNC are also important as that defines the slot length for the data and if you are downconverting from say 24 to 16-bit this is also important, so the device does need both to perform proper estimation and conversion. I would expect that stopping LRCKI alone would trigger the /RDY bit, but this does not seem to be the case. I have not had a chance to test this myself yet, but would suggest instead using 24.576MHz for RCKI to eliminate this as a variable.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Genius 4285 points

    Hi Zak,

    Finally our customer get SRC4192EVM in their hands.

    And had confirmed /RDY flag function as attached image.

    /RDY flag is not "H" when LRCKI or BCKI is stopped, and when restart the clock input /RDY become "H" some period.

    Our customer wants to utilize /RDY signal to MUTE unstable noisy output signal however this behavior cannot avoid noise from speaker.

    Is it possible to duplicate this function in your side?

     

    Regards,

    Mochizuki

    SRC4192 RDY1Dec20.pdf

  • 0 in reply to Mochi
    TI__Mastermind 23050 points

    Hi Mochi,

    I will try to reproduce this behavior in the lab tomorrow!

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Genius 4285 points

    Hello Zak-san,

    Is there any finding in your site?

    Regards,

    Mochizuki

  • 0 in reply to Mochi
    TI__Mastermind 23050 points

    Hi Mochizuki-san,

    I have also observed that the RDY signal is not 100% consistent and is best when used to control MUTE along with the host processor. You should find that if both BCKI and LRCKI are removed that RDY should transition and I don't see how a master device would only stop transmitting one. There is a unique condition though where if both clocks are removed while data is still being transmitted to the input then the RDY pin may not toggle and there will be noise on DOUT so I recommend pulling DIN low before removing input clocks.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Genius 4285 points

    Hi Zak-san,

    Thank you for your effort.

     

    May I conform RDY pin behavior clearly.

    RDY flag is not consistent function if remove either BCKI or LRCKI clock.

    RDY flag work correctly if remove both of BCKI and LRCKI clock.

    Also RDY flag is not toggled while DIN is inputted, no matter what is BCKI and LRCKI condition.

     

    Regards,

    Mochizuki

  • 0 in reply to Mochi
    TI__Mastermind 23050 points

    Hi Mochizuki-san,

    I would say this is close but I want to clarify a bit as the last case is a special condition case:

    1) RDY flag may not change states if only 1 of the input clocks is removed.

    2) RDY flag should work correctly if both BCKI and LRCKI are removed. Typically these are generated together because they are required to be in sync with one another so I can't imagine a practical case where only 1 should be present.

    3) There is a special case where if the input data line is driven when BCKI and LRCKI are abruptly removed it is possible for the RDY pin to have invalid state and for a periodic noise to appear on DOUT. For this reason it is recommended not to remove BCKI and LRCKI until data has finished transmitting and the DIN line has been driven low.

    I would say this is also an unlikely case because generally your data source can't provide data without clocks, but if all input clocks and data in simultaneously stop while DIN is high then this is an abnormal behavior you may observe and I would try to avoid this condition

    Best,

    Zak