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LMK05028: Output 10MHz on all outputs.

Joerg Reins
Prodigy 90 points
Part Number: LMK05028

Hi,

in front of me i have the LMK05028EVM with a 10MHz signal source connected to In1. (LVCMOS 10MHz -> IN1_P; GND -> IN1_N)
In TICSPro i have configured the Chip to output 10MHz everwhere (out 0 to out 7 with default signal routing). 

1) The signal to IN1 is recognized (and chosen -> "REF1VALSTAT" ok)
2) Out0 - Out3 (from PLL2) follow the 10MHz from In1 in phase and frequency which is expected.. (Those outputs come from PLL2)
3) Out4 - Out7 (from PLL1) output "something" close to 10MHz, but it is not in sync with In1.

This is tested by comparing the input with the output on an oscilloscope.
If I trigger on the input and another channel is displaying the output, i expect no waveform movement at the output.
This is true for PLL2 but not for PLL1 despite both showing a frequency lock.

In fact PLL1 only complains about "loss of phase lock", but not "loss of frequency lock" despite the frequency is clearly off, so it cant have a lock to anything. The chip lies.
PLL1 is also not locked to the on-board 10Hz ref clock, since the frequency is pretty close to the provided 10MHz at In1.

Can please someone give me a stored configuration that simply outputs 10MHz (generated by PLL1 and PLL2) on all outputs that is derived from a 10MHz input clock?
I think this should be a fairly simple task - for me this is just a test run if i can get the basics configured, but i clearly cant.

I am not sure how i am supposed to attach a file here - i would like to share my configuration myself.

  • 0
    Prodigy 90 points

    The 10Hz is a typo.. Everything is MHz. I also found the "insert file" button. Here is my config.https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/48/Test.7z

  • 0 in reply to Joerg Reins
    TI__Mastermind 32575 points

    Thanks for your inquiry.  Please give me time to check your configuration file and send a revised file that has been verified.

    Alan

  • 0
    TI__Mastermind 32575 points

    Joerg,

    One problem was that VCO1 frequency was chosen as 4800 MHz and XO is ~48 MHz, this would cause APLL1 fraction operate near the integer boundary which limits the DPLL's tuning range of the APLL1 loop and thus prevents proper DPLL closed-loop operation.  In STEP 5, you can manually enter (force) the VCO1 frequency as "5e9" with PLL1_P1 set to 4, instead of using the initially calculated VCO1 frequency of 4800 MHz.

    I'm attaching a revised configuration file with VCO1 frequency set to 5 GHz and PLL1_P1 set to 4.  I verified this configuration locked on the default EVM using the on-board TCXO and XO.  I reduced the DPLL bandwidth to 4 Hz for better jitter attenuation of the reference input.  

    Instead of 10 MHz TCXO, you may consider using a 12.8 MHz TCXO which would reduce the beat frequency caused by coupling between the synchronous 10 MHz reference input and output clock domain and the free-running 10 MHz TCXO domain.

    Alan

    LMK05028_3loop_DpllBw=4Hz_TcxoBw=200Hz_RefIn1=10M_Tcxo=10M_Xo=48M_Out0to7=10M.tcs

  • 0 in reply to Alan O
    Prodigy 90 points
    Thank you! I can verify that this now works. Very cool.