Wanting to use the LMK00334RTVRQ1 as a clock mux/buffer for PCIe 2.0.
What is the 2.0 additive jitter max and typical for the high and low frequency bands with an HCSL clock output?
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Hi Jack,
Please take a look at this blog post: https://e2e.ti.com/blogs_/b/analogwire/archive/2014/03/28/how-to-optimize-clock-distribution-in-pcie-applications
Table 4 is of particular interest.
Kind regards,
Lane