WEBENCH® Tools/LMK03328: PLL loop filter design for LMK03328

Nimrod Natan

Part Number: LMK03328

Tool/software: WEBENCH® Design Tools

Hello,

How can I design a PLL loop filter for LMK03328 now that Webench Clock Architect is at EOL? Do you have any replacement?

over 5 years ago

0 Hao Z over 5 years ago

TI__Mastermind 18070 points

Hello,

The wizard page in LMK03328 can create loop filter settings for you. Alternatively, you can download PLLatinum sim http://www.ti.com/tool/PLLATINUMSIM-SW and select "custom" in device selection.

Regards,
Hao

0 Nimrod Natan over 5 years ago in reply to Hao Z

Prodigy 60 points

I see no wizard page in the LMK03328.If you are referring to TICS PRO wizard it does not suggest any loop filter values.

Regarding the Pllatinum software, I tried it on "custum" but it does only simulate the path to the VCO output, not the full path. And it does not take into account the input clock.

0 Hao Z over 5 years ago in reply to Nimrod Natan

TI__Mastermind 18070 points

Hi Nimrod,

Please download the latest version of Ticspro. I remember that the wizard was added around July last year.

Regards,
Hao

0 Nimrod Natan over 5 years ago in reply to Hao Z

Prodigy 60 points

Hi,

I have the latest TICS PRO and I see the wizard but it does not suggest any loop filter parameters.

0 Hao Z over 5 years ago in reply to Nimrod Natan

TI__Mastermind 18070 points

Hello,

The wizard will automatically update the loop filter settings along with frequency plan. The loop filter setting is optimized for 12kHz to 20MHz jitter. If you do want to simulate loop filter, you can do that in Ticspro, and it does have the option to take into account the input noise, if that's what you mean:

It also includes output divider, not just up to VCO

Regards,
Hao

0 Nimrod Natan over 5 years ago in reply to Hao Z

Prodigy 60 points

Thanks,

Is this screenshots from PLLatinum?

Do you suggest to put VCO noise on disable?

0 Hao Z over 5 years ago in reply to Nimrod Natan

TI__Mastermind 18070 points

Hello,

Yes this screenshot is from PLLatinum sim, that was a typo. Currently for LMK03328, PLLatinum sim can only be used to simulate loop bandwidth, phase margin and so on. Phase noise and jitter can't yet be simulated because related data haven't been entered into database. The Ticpsro default loop filter setting is sufficient to produce 12k-20MHz integrated jitter displayed in the datasheet.

Regards,
Hao

Clock & timing

Clock & timing forum

WEBENCH® Tools/LMK03328: PLL loop filter design for LMK03328