LMK05028: Assertion of STATUS signal

Hi Taka, 

First note, STAT0 cannot be under "LOR_MISSCLK1". For status signal, it's individualized to each REF. So the options that are available are: 

- REF0 Miss Clk Monitor 

- REF1 Miss Clk Monitor 

- REF2 Miss Clk Monitor 

- REF3 Miss Clk Monitor

The way this signal works, is that when missing clock is triggered, it will be high and when missing clock is not triggered it will be low. So for example if you're using a 25 MHz reference input (as long as the reference monitors are updated accordingly on the Main start page - a simple frequency input into the field and a enable/disable of the missing clock would do this, or a runscript) and provide a 25 MHz clock into the input, the signal would be low. Change to 20 MHz and the signal will be high. Change back to 25 MHz signal will be low. 

This a live update and this does not match the interrupt bit. The status signal will match the live status register status. Interrupt bits or sticky bits as they're called, once triggered, they're latch and need to be manually cleared in order to measure again essentially. So for the same example above, 25 MHz reference input configuration, start at 25 MHz clock, LOR_MISSCLK_INTR will be low, change to 20 MHz LOR_MISSCLK_INTR will be high, change back to 25 MHz LOR_MISSCLK_INTR will remain high since this is latched now and requires a clear.

The live reading however will be updating live. 

Thanks and regards,

Amin 

Hi Amin,

Thank you for your answer.

If that's the case, STATUS[1:0] and GPIO[6:5] signals can be configured to both status signal and interrupt flag.

Status signal is directly linked to DPLL monitors and interrupt flag derives from the live status registers with INTR registers.

And status signal can not keep asserting if input reference clock turns to available.

Is my understanding correct?

Best regards

Taka

Hi Taka, 

I'm not sure I understand your question... 

Status signal will mimic live register readback. If live registers show something, status signal will match it exactly at that time. 

Interrupt signals tell you whether at any point from the last time it was cleared to now that you're performing the readback, was the particular signal ever high or triggered. 

Status [1:0] and GPIO [6:5] can be configured to show live status only. They cannot show interrupts as they continuously update. 

Regards, Amin 

Hi Taka, 

All interrupt signals are available as live signals as well. That comment implies that the options/selections that are available, for example a DPLL LOFL or a REF0 MISS CLK, are the same. If you look in the GUI, you will see that the 2 columns have both. 

The GUI will also have the full list of what can be brought out onto status/GPIO channels (3rd box in the picture above, drop down menu). These will all be live readbacks. They will update to what current state is. They will not get latched and stay in a current condition as the interrupts do.

If you connect a STAT0 output to an oscilloscope, and STAT0 is configured under REF0 MISS CLK, and you change the input frequency into REF0 you will see the signal go up and down, depending on whether missing clock gets triggered or not. So during the first trigger, it is showing you what the interrupt flag will be showing you, but unless you clear the interrupt, once you come back valid, the interrupt will remain latched while the live will show valid as will your output on the oscilloscope from STAT0.  

Regards, Amin 

Hi Amin,

Do you mean even if Sticky Status is valid, STAT0 signal doesn't keep asserting flag although a INTR register holds that status?

If this is correct, how long does STAT0 assert the flag?

I have one more question.

If I configure STAT0 to output  REF0 MISS CLK, do I have to place a check mark in any box, probably LOR_MISSCLK, on GUI?

My understanding is that  even if I don't place a check mark any box, STAT0 asserts flag, but I can't confirm the status of live registers. 

Best regards

Taka