Other Parts Discussed in Thread: LMK04821, LMK04826
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No external VCO or crystal. CPOUT (pins 32, 46) disconnected, CLKin1 (pins34, 35) disconnected, OSCOUT (pins 40, 41) disconnected.
CLKin0 (pins 37, 38) connected to OSC XO 125.000MHZ LVDS SMD
Optionally, to OSCin (pins43, 44) can be connected anther one OSC XO 125.000MHZ LVDS SMD
Look at: PLL_CONFIG_0817(1)0.csv.
Column B: reading from default after power up.
Column C: Desirable changes. For example:
Line 323: PLL_SPI_LOCK_LSB = 83
Line 219: PLL_SYNC_FIX_127 = 127
Line 229: PLL_CLKin_SEL_MODE = 0. We do not need to use external control, but pins CLKin_SEL0, CLKin_SEL1 connect to pins of Cyclone 4. There is “0”
Line224: PLL_CLKin1_EN = 0 (PLL_CLKin0_EN=1)
Line 26: PLL_DCLKout4_DIV = 2. The output we use for control of output Frequency. After “set PLL“, we get 593MHz. (PLL_DCLKout4_DIV = 1; 793MHz)
In this case, If line 186 PLL_Feedback_Mux = 1, PLL_DCLKout4_DIV = 2; 750 MHz. If PLL_DCLKout4_DIV = 1, it will be 1GHz
Now, after “Get PLL” we get column “D”. The question is:
- Line 235: PLL_CLKin_SEL0_TYPE became =4. It is output. How it is possible? It had been programmed to be input with purpose, because it is connected to another output. ?
- Line 219: It is Fixed register. Why it is reassigned to another number?
- Why it is insistently change line 224 PLL_CLKin0_EN = 1 to 0, and PLL_CLKin1_EN = 0 to 1?
- Why dividers lines 24 – 30 change value?
Really, we need for one output have frequency f1 = 2GHz +/- 150MHz, and for another output - exactly f2 = f1/2. What combination of register values will provide such a frequency?