Part Number: LMK05028
My customer has a Gigabit PHY that is time synchronized using IEEE-1588. It outputs a 1 Hz Pulse Per Second. They would like to synchronize their 25 MHz system clock to this PPS signal.They plan to run our AM3359 PRU Real Time Ethernet at 8 KHz. The PRU SYNC0 signal run through a PLL on each device. This is programmed to produce a configurable clock, depending on the slave device type and conversion rates. (600KHz - 8.192 MHz). The PRU will keep the slave devices from drifting apart, but the PRU itself will drift with respect to the grandmaster time unless it is driven with a PTP disciplined clock.
I looked at the LMK05028 synchronizer clock, but I don’t have much experience with these advanced PLL chips.
Any recommendations? (Preferably small form factor)
A block diagram may be helpful to me here. I want to be sure I understand the frequency plan, you have one input and three outputs:
1 PPS input, from Gigabit PHY synced to IEEE-1588: 1x8 kHz output, for AM3359 PPU Real Time Ethernet device: 1x600 kHz to 8.192 MHz output, PRU SYNC0 signal: 2x
You mention one PLL for each PRU SYNC0 signal.
* How does the PRU keep the slave devices from drifting apart? Will it apply DCO to the PLL driving it?
* For the 600 kHz to 8.192 MHz, is there a set of frequencies they are picking from or could it be just any frequency. Is there any frequency accuracy requirement on these outputs?
* If there are two PLLs for the PRU SYNC0 signal, is it ok for the 8 kHz output to share frequency domain with one of these PLLs?
More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html
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