Part Number: LMK04832EVM
I am now testing the evaluation board of the LMK04832 device.
I want to connect it to a spectrum analyzer to measure its phase noise.but the outputs of the PLL are not RF. They are PECL, LVDS, CML or LVCMOS.
How should I connect the output to a spectrum analyzer to measure phase noise?
One more question.
If i want to connect the LMK04832 device to more than 7 JESD204B devices (working at subclass 1) and I want that the clock to all devices will be 0 phased synchronized. How would you recommend me to do it?
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In reply to Yuval Minster:
In my design I plan to connect the LMK04832 CLK out to the A2D ADS54J60.
I read in the PLL data sheet that the clock delay+divider can be bypassed (section 126.96.36.199). This will give me high performance. The problem is that In this mode, the only usable output format is CML
The ADS54J60 clock inputs format is LVDS, LVPECL or Sine wave (all AC coupled) - no CML is mentioned.
Can't I use the CML PLL clock output to the A2D ?
Yuval MinsterHow should I connect the output to a spectrum analyzer to measure phase noise?
You have a few options:
Yuval MinsterIf i want to connect the LMK04832 device to more than 7 JESD204B devices (working at subclass 1) and I want that the clock to all devices will be 0 phased synchronized. How would you recommend me to do it?
We have many suggestions for synchronizing multiple devices in the Multi-Clock Synchronization application note and accompanying slideset. Please review this material first.
Yuval MinsterCan't I use the CML PLL clock output to the A2D ?
Technically, the maximum frequency to the ADS54J60 is only 1000MHz, so unless you plan to use the LMK04832 in distribution mode, high performance CML bypass mode will only operate at frequencies above the usable clock frequency of the ADS54J60. Furthermore, below 250MHz, LVPECL and CML noise floor performance are equivalent.
If you do plan to use distribution mode for a clock above 250MHz to the ADS54J60, the CML clock amplitude will be effectively equivalent to the LVPECL amplitude. As long as you AC-couple the CML clock (a configuration which is endorsed by the ADS54J60 datasheet in figure 148), connecting a CML clock to the ADS54J60 is acceptable.
In reply to Derek Payne:
I am trying to work with the LMK04832 evaluation board but until now with no success.
For the beginning i just wanted to see a clock at the output by scope but for some reason i do not see anything.
This is what i did:
1. I connected a 122.88MHz, 5dBm sine wave to CLK1
2. I used the TICS to program the device to the default values.(the clock distribution is 2949.12MHz)
3. The LED is on so i know that the PLL is locked
4. I programmed Clock out 9 to be active, CMOS (Norm/Norm) and set it to ~134M by changing the divider to 22.
5. I connected the output to a scope but i don't see any signal
Do you know what i did wrong?
Can you save the configuration you tested as a .tcs file using TICS Pro "File -> Save" menu, and post it for review?
CLKout8_9_PD must be set to 0 (unchecked) to power up CLKout9.
I unchecked the PD pin and i now see a CMOS signal at the output.
I have few more questions:
1. the CMOS output does not looks good (bad SI), see attached. Is it because the 240 ohm to GND ?
2. I changed the output to PECL or CML but in this case i do not see any signal on the scope. Do you know why?
The default CLKout9 configuration does not have any external termination, just AC-coupling capacitors. The LVCMOS signal is not being corrupted due to alternate termination. In my experience, LVCMOS over long cable runs and with no series damping tends to see distortion like what is pictured above. If you can reduce the distance traveled by the LVCMOS signal to the oscilloscope, or add a small series resistance (e.g. a 3dB pad), you should see the quality of the signal improve somewhat. Also, I'm not sure what bandwidth your oscilloscope has; I suspect it should be sufficient to monitor an 80MHz signal, but it is worth double-checking that your bandwidth is about 5x the highest frequency observed, to ensure your edges are not distorted due to higher order harmonic losses.
Because there's no termination on CLKout9 by default, there's no way a PECL or CML termination would work on CLKout9 - you must install PECL termination (e.g. 240Ω to GND, or 50Ω to VCC - 2V) to get PECL output, or CML termination (50Ω to VCC, or 68nH + 2x20Ω to VCC for slightly improved EVM/bondwire matching) for CML output.
I understand my mistake. I looked at CLK0 in the design and since it has a 240 ohm resistor to GND, I assumed that all channels are the same. Since it isn't, i looked at CLK0 and saw a LCPECL clock.
I connected it to Spectrum analyzer (Rohde and Schwarz model FSW) and measured 3 types of frequencies: 737.28M, 1474.56M and 2949.12M.
I measured phase noise (1KHz to 10M offset) and insert the results to a "phase noise to jitter calculator".
The calculator gave me 3 results: phase jitter, period jitter and cycle-cycle jitter
For the 737.28M the results were: phase jitter 75fs, period jitter 100fs and cycle-cycle jitter 180fs
For the 1474.56M the results were: phase jitter 78fs, period jitter 140fs and cycle-cycle jitter 250fs
For the 2949.12M the results were: phase jitter 1.082ps, period jitter 18.5ps and cycle-cycle jitter 32.06ps
1. When you write in the data sheet RMS jitter do you mean phase jitter, period jitter or cycle-cycle jitter
2. My jitter results are worst than yours and it increases as I increase the CLKout frequency. What do you think is the reason for that (the spectrum analyzer should not be the problem)
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