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LMK05028: LMK05028 Application Issue when Spur Comes with REF Input

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Replies: 13

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Part Number: LMK05028

Hi Team,

My customer is using LMK05028. We found one unlock issue. The REF input is 10M. And when there is a spur locate at 30.72M and the power is ~-40dBm, the LMK05028 is unlock. When remove the spur, it locked again. We suspect that the device's rejection of the spur is not strong enough. Need to check with you, if there is a way to increase the rejection of the spur's influence at LMK05028 side. Thanks!

  • Hello, 

    How is the spur "removed"? This implies we know what is the source of the spur, so I need to know what it was to introduce it. 

    Secondly, when mentioning unlock, we need to clearly what was unlocked. I assume this is only looked at witch the output connected to an equipment, so when unlock implies the device is no longer outputting. This would mean APLL has gone out of lock after locking, which doesn't make any sense. 

    I'm emphasizing this because DPLL can also go unlock, for example when the reference is removed, and the output should maintain because APLL is locked. 

    So please provide what is the source of the spur and how were you able to remove it. Secondly, what specifically is going "unlock". 

    Thanks and regards,

    Amin 

  • In reply to Amin Eshraghi:

    Hi Amin,

    Sorry for the misunderstanding. This spur is from another clock device coupling by space. And removed by switching off the clock device. By saying "unlock", I mean that the DPLL2 is unlocked. We also set the 0xBB to be 0xd, but it seems that it didn't work, the DPLL2 is still unlock when spur comes.

    We want to know if there is a config that can avoid the unlock when spur comes.Thanks.

  • In reply to Qiang Ren:

    Hi, 

    So the spur observed at an output from the DPLL2/APLL2 loop, causes DPLL2 to be unlocked? This spur is from another device that's on the board. Is this device close to the reference input? 

    To understand what's causing the DPLL2 to unlock, we need to know a few things, is the reference DPLL2 trying to lock to, valid? Does DPLL2 select that reference? Here's the GUI image where this data can be found, if you hover over it it will also tell you register numbers and bits that correspond to this info: 

    If the reference is invalid - we'd need to understand what part of the validation checks is causing to become invalid when the spur is there. 

    If it is valid, the DPLL should be locked unless it's a bad configuration. Which shouldn't be the case since you mentioned if there's no spur the DPLL is locked. 

    Thanks and regards,

    Amin 

  • In reply to Amin Eshraghi:

    Hi Amin,

    30.72M comes to the device by the REFIN0 and you can find the tcs files as attached.

    When there is no spur and input 10M 0dBm reference into REFIN0, the register status is as below:

    0x2E6 -- 0x30 

    0x2FF-- 0x02

    0x303--0x01

    DPLL2 loss of lock: 0  DPLL2 lock

    DPLL2  REF0 selected 1 selected 

    When there is 30.72M spur and input 10M 0dBm reference into REFIN0, the register status is as below:

    0x2E6 -- 0x20

    0x2FF-- 0x02

    0x303--0x00

    DPLL2 loss of lock: 1  DPLL2 unlock

    DPLL2  REF0 selected

    After removing the 30.72 spur, the register status change to the status in the 1st step(no spur status).

  • In reply to Qiang Ren:

    Hello, 

    Thank you for the information and sharing the .tcs file. So when the spur is there, it's IN0 is no longer valid. 

    I noticed in your .tcs file that IN0 can support either DPLL1 or DPLL2 based off of inputs however for DPLL reference selection only IN0 has a priority. If this is changed, the DPLL2 can lock to IN1 as well. How to update the priority selection in the GUI with image at the bottom of the email. 

    The question of why IN0 becomes invalid and IN1 remains valid is understood now as well. IN0 has PPM detector enabled. Not sure what the requirements for the system are... but you can disable IN0 PPM detector or at least increase the invalid threshold. The spur is causing enough noise where this is becoming invalid. 

    On a similar note, I would advise that missing clock is enabled - there's no harm in this and it would allow DPLL to realize a loss of reference much faster and enter holdover before corruption or large frequency error can occur. 

    Thanks and regards,

    Amin 

    DPLL2 Auto Priority change: 

    PPM detect and missing (late/early) clock detect 

  • In reply to Amin Eshraghi:

    Hi Amin,

    1. LMK05028 IN0 from EXT 10MHz input,lmk05028 IN1 from lmk05028 out0 10MHz 1/2  Vpp, so we can just check DPLL2 IN0.

    2. You can find the tcs file as attached (lmk05028 BTS 10Hz fae 1016)

    disable Valid IN0,

    Enable  missing clock (when late clocks =0, input check is valid, so set it to 1 )

    Enable  runt pulse 

    3. When there is no spur and input 10M 0dBm reference into REFIN0, the register status is as below:

    0x2E6 -- 0x30 

    0x2FF-- 0x02

    0x303--0x01

    DPLL2 loss of lock: 0  DPLL2 lock

    DPLL2  REF0 selected : 1 selected 

    4. When there is 30.72M spur, reg is as below(no change of the reg,DPLL2 unlock):

    0x2E6 --0x30

    0x2FF-- 0x02

    0x303--0x01

    DPLL2 loss of lock: 1  DPLL2 unlock

    DPLL2  REF0 selected : 1 selected 

    When switch off the spur, the reg recover to the status when there is no spur

    5. When enable missing clock late clocks=0, and 10M 0dBm ref input to refin0 and no spur:

    0x2E6 -- 0x20 

    0x2FF-- 0x02

    0x303--0x00

    DPLL2 loss of lock: 0  DPLL2 lock

    DPLL2  REF0 selected : 0

    lmk05028 BTS 10Hz ae 1016.tcs

  • In reply to Qiang Ren:

    Hello, 

    Thanks for the details. I would just like to confirm I understand correctly: 

    1. No spur - DPLL1 selects REF1 and DPLL2 selects REF0 - both locked 
    2. Spur added - DPLL1 selects REF1 and locked - DPLL2 has REF0 as valid and selected, but DPLL2 is not locked
      1. This is with no input validation enabled basically, correct? Since next step is saying Late and Early enabled.. I'm assuming this is with no PPM detector and no missing clock, so really input may be valid but in actuality we're not running it through any validation
    3. Final case: Enabling missing/early - only REF1 is considered valid (REF0 isn't valid) - DPLL1 selects REF1 and is locked - DPLL2 is showing locked yet the reference selection is "holdover" 
      1. Loss of lock is only tied to frequency lock and therefore will no get flagged if device was previously locked 

    One more thing I've noticed, why is the output type CMOS (+/+) yet input is AC-DIFF(ext. Term). CMOS (+/+) would provide outputs with both n and p in phase.

    • If using singled ended input, you can change the selection to LVCMOS and the change the channel output to CMOS (+/Hi-Z) or vice versa since only 1 channel would be needed. 
    • If using differential, then output type should be changed to a differential type (LVDS, CML, LVPECL) 

    Thanks and regards,

    Amin 

  • In reply to Amin Eshraghi:

    Hi, 

    One more thing that's confusing, the picture is contradicting what I've took to understand. OUT0 is feeding IN1 which is going to DPLL1 - so OUT0 cannot impact DPLL2 in any way. In the picture you have DPLL2 is just using IN0 which is an external reference. 

    The output type update still applies though - OUT0 CMOS (+/+) will be worse in terms of both performance and spur as well. So perhaps that change can fix the system. 

    Thanks and regards,

    Amin 

  • In reply to Amin Eshraghi:

    Hi Amin,

    Please see the response as below:

    Thanks for the details. I would just like to confirm I understand correctly: 

    1.    No spur - DPLL1 selects REF1 and DPLL2 selects REF0 - both locked   

    —— yes

    2.    Spur added - DPLL1 selects REF1 and locked - 

    ——  Spur added - DPLL1: lock; DPLL1 ref1 selected :lock (when frequency detect threshold disable,if  enable is unlock)

         DPLL2 has REF0 as valid and selected, but DPLL2 is not locked

    ——Spur added - DPLL2: unlock; DPLL2 ref0 selected :lock (when frequency detect threshold disable,if  enable is unlock)

    1.    This is with no input validation enabled basically, correct?

    ——  yes

     Since next step is saying Late and Early enabled.. I'm assuming this is with no PPM detector and no missing clock, so really input may be valid but in actuality we're not running it through any validation

    —— frequency detect threshold disable, Late and Early enabled :  the result  same ;Spur added and frequency detect threshold enable,the DPLL2 REF0 selected  :invalid

    3.    Final case: Enabling missing/early - only REF1 is considered valid (REF0 isn't valid) -DPLL1 selects REF1 and is locked -

                ——   yes

       DPLL2 is showing locked yet the reference selection is "holdover" 

       ——   Spur added,DPLL2 showing  unlock,APLL2 is lock ; DPLL2 reference selection  "holdover" 

    1.    Loss of lock is only tied to frequency lock and therefore will no get flagged if device was previously locked 

    —— yes

    One more thing I've noticed, why is the output type CMOS (+/+) yet input is AC-DIFF(ext. Term). CMOS (+/+) would provide outputs with both n and p in phase.

    ——one CMOS+ to lmk05028 IN1, other cmos+ to lmk04821 refin0

    o  If using singled ended input, you can change the selection to LVCMOS and the change the channel output to CMOS (+/Hi-Z) or vice versa since only 1 channel would be needed. 

    o  If using differential, then output type should be changed to a differential type (LVDS, CML, LVPECL) 

    ——    using differential,the refinput  detect sometime is inaccuracy,so TI FAE advise set  differential type  (AC-DIFF interface Type), REFIN1  can change the selection to LVCMOS input ,results still the same

    One more thing that's confusing, the picture is contradicting what I've took to understand. OUT0 is feeding IN1 which is going to DPLL1 - so OUT0 cannot impact DPLL2 in any way. In the picture you have DPLL2 is just using IN0 which is an external reference. 

    ——  DPLL2 is just using IN0 which is an external reference,   DPLL1 is just using IN1 which is from LMK05028 OUT0+; DPLL2  impact DPLL1 

    The output type update still applies though - OUT0 CMOS (+/+) will be worse in terms of both performance and spur as well. So perhaps that change can fix the system. 

    ——  Clock inputs IN0/IN1 interface Type set to  LVCMOS/LVCMOS (or other type), results still the same.

    1. Spur added,frequency detect threshold disable,  10MHz  still 5dBm,  lmk05028 has some  filter ciruit to rejector spur ? 

    2, Spur added, reset DPLL2 (0x02a5 02-0x02a5 00;0x006003,0x006002),results still the same