LMH1983: Address 0x15 Loss of Alignment Control bit 2:0,

Hi Mita, 

Register 0x15 determines the threshold for what's considered aligned or not aligned. In always align mode, if the misalignment is detected, the device will force an alignment. Register 0x15 is never ignored, it has a preset condition or it can be user defined. Here's the section of the datasheet that goes over this information: 

8.3.10 TOF1 Alignment 

...

The alignment between the incoming FIN and the TOF1 output may be controlled in a number of ways. There are three different alignment modes in which TOF1 may operate as selected via Register 0x11:

1. 11'b (default): PLL1 never attempts to align.

2. 10'b: PLL1 always forces alignment to FIN.

3. 00'b: Automatically force alignment to FIN when they are misaligned.

Misalignment can be defined by the user via Register 0x15. In Register 0x15, a time window is defined to specify the amount of mismatch permitted between FIN and TOF1 while still considering them to be aligned. If the input reference signal has a significant amount of low frequency jitter or wander, it may be possible for the relative alignment between TOF1 and FIN to vary over time. Selecting "Always Align" mode may lead to undesirable timing jumps on the output of CLKout1/TOF1.

Once the device decides that it needs to align TOF1 and FIN, there are two ways that it can be done. Crash lock involves simply resetting the counter that keeps track of where the TOF1 output transition happens, resulting in an instantaneous shift of TOF1 to align with FIN. Drift lock involves using the second loop in PLL1 and skewing the VCXO to make the frequency of CLKout1 either speed up or slow down. The VCXO skewing slowly pulls TOF1 and FIN into alignment. If a new reference is applied that is not in alignment with TOF1, but the output is currently in use, it may be better to slew TOF1 into alignment rather than to cause a major disruption in the timing with a crash lock. The LMH1983 allows the user to select either crash lock or drift lock, controllable via Register 0x11. The option of crash lock or drift lock is available when the difference in phase is small (Output <2 LOA_window x 27 MHz Clock) and when the difference in phase is large (Output > 2 LOA_window x 27 MHz Clock). Furthermore, if the difference is large, the user can tell the device to achieve alignment either by advancing or retarding the phase of PLL1. Note that if the difference in alignment is large, achieving alignment via drift lock may take a very long time (tens of seconds), during which the output clock will not be phase locked to the input HIN.

Thanks and regards,

Amin

Hi Mita-san, 

Let me try to make it more clear hopefully. 

Always align causes the PLL/TOF counters to be reset at every reference frame (Fin) pulse.  Selecting "Always Align" mode may lead to undesirable timing jumps on the output of CLKout1/TOF1.

While auto align gets initiated when misalignment is detected. Misalignment is determined by the LOA_Window register.  

Thanks and regards,

Amin

Hi Mita,

I'm jumping in to help clarify your understanding of the device. Hopefully I can answer your questions.

Let me first respond to your original questions. Let me know if you had additional questions as well.

A1: LOA window setting of register 0x15 is only used when register 0x11[3:2] = 0b01 as indicated on datasheet pages 18-19 and 28. 

Agreed, if you are using 0x11[5:4] = 0b10 (Always Align), the device will always align regardless of the misalignment. For Auto Align, you must define the misalignment in 0x15.

A2: Yes, that is correct

Kind regards,
Lane