Part Number: LMH1983
Please advise me on my question bellow.
I thin you can adjust the loss of align threshold through the
register address 0x15 Loss of Alignment Control bit 2:0.
In the mean time this device has two align mode, such as
Always align mode and Auto align mode.
I suppose that in Auto align mode , the device activates align process
when input and output video timing difference excess some threshold.
Q1. Does the register address 0x15 Loss of Alignment Control bit 2:0,
determines this threshold? .
I suppose that in Always align mode, the device activates align process
Regardless of input and output video timing difference.
Q2. Is the register address 0x15 Loss of Alignment Control bit 2:0,
Ignored in Always align mode? .
Register 0x15 determines the threshold for what's considered aligned or not aligned. In always align mode, if the misalignment is detected, the device will force an alignment. Register 0x15 is never ignored, it has a preset condition or it can be user defined. Here's the section of the datasheet that goes over this information:
8.3.10 TOF1 Alignment
The alignment between the incoming FIN and the TOF1 output may be controlled in a number of ways. There are three different alignment modes in which TOF1 may operate as selected via Register 0x11:
1. 11'b (default): PLL1 never attempts to align.
2. 10'b: PLL1 always forces alignment to FIN.
3. 00'b: Automatically force alignment to FIN when they are misaligned.
Misalignment can be defined by the user via Register 0x15. In Register 0x15, a time window is defined to specify the amount of mismatch permitted between FIN and TOF1 while still considering them to be aligned. If the input reference signal has a significant amount of low frequency jitter or wander, it may be possible for the relative alignment between TOF1 and FIN to vary over time. Selecting "Always Align" mode may lead to undesirable timing jumps on the output of CLKout1/TOF1.
Once the device decides that it needs to align TOF1 and FIN, there are two ways that it can be done. Crash lock involves simply resetting the counter that keeps track of where the TOF1 output transition happens, resulting in an instantaneous shift of TOF1 to align with FIN. Drift lock involves using the second loop in PLL1 and skewing the VCXO to make the frequency of CLKout1 either speed up or slow down. The VCXO skewing slowly pulls TOF1 and FIN into alignment. If a new reference is applied that is not in alignment with TOF1, but the output is currently in use, it may be better to slew TOF1 into alignment rather than to cause a major disruption in the timing with a crash lock. The LMH1983 allows the user to select either crash lock or drift lock, controllable via Register 0x11. The option of crash lock or drift lock is available when the difference in phase is small (Output <2 LOA_window x 27 MHz Clock) and when the difference in phase is large (Output > 2 LOA_window x 27 MHz Clock). Furthermore, if the difference is large, the user can tell the device to achieve alignment either by advancing or retarding the phase of PLL1. Note that if the difference in alignment is large, achieving alignment via drift lock may take a very long time (tens of seconds), during which the output clock will not be phase locked to the input HIN.
Thanks and regards,
We are glad that we were able to resolve this issue, and will now proceed to close this thread.
If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.
In reply to Amin Eshraghi:
Thank you for your feedback.
Let’s focus on the differences between Always align and Auto-align
I suspect that the device tris to keep align between FIN and TOF1 “before”
Timing difference of FIN and TOF1 hits the threshold specified the LOA_Window
in address 0x15.
Otherwise, the device toggle between Aligned and Los of Align state.
I suspect that in Always align mode, align process is activated regardless
of timing difference between FIN and TOF1.
And in Auto align mode align process is activated if timing difference between
FIN and TOF1 exceeds some threshold but it is not equal to LOA_Window.
Please check it with design document.
In reply to user4779049:
Let me try to make it more clear hopefully.
Always align causes the PLL/TOF counters to be reset at every reference frame (Fin) pulse. Selecting "Always Align" mode may lead to undesirable timing jumps on the output of CLKout1/TOF1.
While auto align gets initiated when misalignment is detected. Misalignment is determined by the LOA_Window register.
I understand that in Always align mode, align process occurs every top of frame, and frame counter may be reset
if it is in Crash lock mode.
However, I don't think that it may lead to undesirable timing jumps on the output of CLKout1/TOF1 even though in
Always align and in Crash lock as long as timing delta of the REF and TOF1 is smaller than one 27 MHz clock period, ,
because, CLK1 is buffered output of the VCXO and may not be corrupted by the reset action.
What do you think of it?
Regarding to the Auto align mode, I suspect that align activity may occur before the device detects
loss of align, because device is expected to keep align.
If the timing delta of the REF and TOF1 exceeds LOA_Window register, it results Loss of align.
I don't see any reference to this "before" that you're talking about. Not sure how an alignment could be initiated if no misalignment is detected.
With regards to the undesirable jumps, I have to based this off of what the datasheet provides and it clearly identifies this as a possible outcome. Both in:
"Selecting "Always Align" mode may lead to undesirable timing jumps on the output of CLKout1/TOF1."
"Furthermore, if the difference is large, the user can tell the device to achieve alignment either by advancing or retarding the phase of PLL1. Note that if the difference in alignment is large, achieving alignment via drift lock may take a very long time (tens of seconds), during which the output clock will not be phase locked to the input HIN."
Regarding to the topic “before”, in general, in PLL system, phase correction
action would be done before PLL loses lock to maintain lock condition.
I anticipate that video phase align in LMH1983 uses the same mechanism as PLL
Phase correction must be done before the loss of align.
I hope you check it with design document instead of the description on the datasheet.
On the second topic, "CLK1 is distorted (or corrupted)", I heard that CLK1 is buffered
output of the VCXO. If so, CLK1 may not be corrupted regardless of RESET PLL1.
Can you please check it referring the design document.
I agree that TOF1 may be corrupted by the TOF1 align process if video phase difference is
Larger than one 27MHz clock period.
I am looking forward your response.
I appreciate it if you can give me answer to my question
I'm jumping in to help clarify your understanding of the device. Hopefully I can answer your questions.
Let me first respond to your original questions. Let me know if you had additional questions as well.
A1: LOA window setting of register 0x15 is only used when register 0x11[3:2] = 0b01 as indicated on datasheet pages 18-19 and 28.
Agreed, if you are using 0x11[5:4] = 0b10 (Always Align), the device will always align regardless of the misalignment. For Auto Align, you must define the misalignment in 0x15.
A2: Yes, that is correct
More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html
Learn more about clocking fundamentals by watching the TI Precision Labs: https://training.ti.com/ti-precision-labs-clocks-and-timing
In reply to Lane Boyd:
Thank you for the answers.
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.