LMX2572: Category 3 Phase SYNC and full assist VCO Calibration

Chuck,

Normally this refers to the total analog lock time. If the VCO has already been calibrated or if calibration is being assisted then typically the default setting of MASH_RST_COUNT=50000 is worst case 250µs (200MHz OSCin), which is almost always several times larger than the settling time to 1Hz accuracy. On the other hand, if this includes VCO calibration time without assistance, in some cases the total analog lock time can be a few hundred microseconds.

In practice, the actual lock time for the purposes of MASH reset should be taken as the point where no cycle slipping can occur. So 1Hz settling time is typically a vast overestimate of the analog lock time. The presence or absence of cycle slip depends on the loop bandwidth, the phase detector frequency, and the required change in frequency, and normally the process of VCO calibration places the VCO output frequency within 20MHz of the final frequency, so the potential for cycle slip is limited; however, if the loop bandwidth is very small relative to the phase detector frequency, cycle slip is possible.

Again, it would be helpful if I could see the register programming you are using.

Regards,

Hi Derek,

Here is the register programming we are using at 2408 MHz.  We are seeing three possible phase states after asserting the hardware SYNC signal. We checked the timing of the SYNC relative the 100 MHz clock, and we see optimum timing per the data sheet requirements.  We have an LMX2594 located on the same PCB driven from the same clock and SYNC signals; and it SYNCs reliably.   

Best Regards,

Chuck

REG 0x00,6098

REG 0x01,0808

REG 0x02,0500

REG 0x03,0782

REG 0x04,0A43

REG 0x05,38C8

REG 0x06,C802

REG 0x07,00B2

REG 0x08,6800

REG 0x09,0004

REG 0x0A,10F8

REG 0x0B,B028

REG 0x0C,5001

REG 0x0D,4000

REG 0x0E,1878

REG 0x0F,060F

REG 0x10,006D

REG 0x11,012C

REG 0x12,0064

REG 0x13,2707

REG 0x14,5C48

REG 0x15,0409

REG 0x16,0001

REG 0x17,007C

REG 0x18,071A

REG 0x19,0624

REG 0x1A,0808

REG 0x1B,0002

REG 0x1C,0488

REG 0x1D,0000

REG 0x1E,18A6

REG 0x1F,C3E6

REG 0x20,05BF

REG 0x21,1E01

REG 0x22,0010

REG 0x23,0004

REG 0x24,0030

REG 0x25,0305

REG 0x26,0000

REG 0x27,00C8

REG 0x28,0000

REG 0x29,0000

REG 0x2A,0000

REG 0x2B,0020

REG 0x2C,1FA3

REG 0x2D,C61F

REG 0x2E,07F1

REG 0x2F,0300

 REG 0x30,03E0

REG 0x31,4180

REG 0x32,0080

REG 0x33,0080

REG 0x34,0420

REG 0x35,0000

REG 0x36,0000

REG 0x37,0000

REG 0x38,0000

REG 0x39,0020

REG 0x3A,0001

REG 0x3B,0001

REG 0x3C,03E8

REG 0x3D,00A8

REG 0x3E,00AF

REG 0x3F,0000

REG 0x40,1388

REG 0x41,0000

REG 0x42,01F4

REG 0x43,0000

REG 0x44,03E8

REG 0x45,0010

REG 0x46,0000

REG 0x47,0081

REG 0x48,0001

REG 0x49,003F

REG 0x4A,0000

REG 0x4B,0800

REG 0x4C,000C

REG 0x4D,0000

REG 0x4E,0001

REG 0x4F,0000

REG 0x50,0000

REG 0x51,0000

REG 0x52,0000

REG 0x53,0000

REG 0x54,0000

REG 0x55,0000

REG 0x56,0000

REG 0x57,0000

REG 0x58,0000

REG 0x59,0000

REG 0x5A,0000

REG 0x5B,0000

REG 0x5C,0000

REG 0x5D,0000

REG 0x5E,0000

REG 0x5F,0000

 REG 0x60,0000

REG 0x61,0000

REG 0x62,0000

REG 0x63,0000

REG 0x64,0000

REG 0x65,0000

REG 0x66,0000

REG 0x67,0000

REG 0x68,0000

REG 0x69,4440

REG 0x6A,0007

REG 0x6B,8801

REG 0x6C,00A1

REG 0x6D,9D7D

REG 0x6E,0C68

REG 0x6F,0102

REG 0x70,FE6D

REG 0x71,0000

REG 0x72,7802

REG 0x73,0000

REG 0x74,0000

REG 0x75,0000

REG 0x76,0000

REG 0x77,0000

REG 0x78,0000

REG 0x79,0000

REG 0x7A,0000

REG 0x7B,0000

REG 0x7C,0000

REG 0x7D,1F7C

REG 0x7E,0000

REG 0x7F,0000

Hi Chuck,

Are you sure that Cat. 3 phase synchronization is possible with LMX2594 in full assist mode? As far as I know, this is not possible as phase sync requires VCO calibration.

also you said LMX2572 in full assist mode has three different phases after sync, will you get consistent sync if you put it back to no assist mode?

Your register looks fine except for you have the INPIN_IGNORE bit checked, as a result, the sync pulse will be ignored.

Hi Noel and/or Derek,

We have made some progress resolving this problem, although we are not quite  out of the woods yet.  We have set the MASH_RESET_COUNT  values to ensure the delay is longer than the 4x the lock time.  We initially thought the LMX2594 was SYNC 'ing properly, but our conclusion was incorrect.   We believe both the LMX2594 and the LMX2572 are behaving the same way.  We set both devices on frequency and then apply multiple SYNC events (spaced at about 100 mSec intervals) without changing the frequency.  We expect to see a repeatable  phase relationship after each SYNC event.  Here is a summary of our observations:

1)  Both the LMX2594 and the LMX2572 can assume two different phase states after the CAT3 SYNC is applied.  The "primary" phase relationship is repeatable in approximately 99 out of 100 times.  The "alternate" phase state is approximately 1 out of 100 times the SYNC is applied.  The "alternate" phase state is a repeatable value (in degrees). 

2) The calibration data is manually written from memory and forced in both the theLMX2594 and the LMX2572.  This seems to be working correctly. Re-writing the calibration registers after the "alternate" phase state occurs doesn't change the phase relationship.

3) We have verified the integrity of the 100 MHZ OSC_in signal, and the timing requirements of the hardware SYNC signal.  

Any additional suggestions you may have to help us troubleshoot this problem would be greatly appreciated.  This seems to be the last hurdle.

Best regards,

Chuck Beam