Hello,
I would like to know if my circuit is right. Could someone from TI check it please? Also i would especcialy ask about PRI input LVDS buffer. Is it true LVDS input buffer? Cause iam using LVDS because of galvanic isolation and iam not sure if your device needs offset voltage or not. Driver of LVDS clock vill be FPGA Cyclone IV. Also i would like to ask about termination of secondary input where is used CRYSTEK oscilator. [04] - PLL.PDF