• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 21 subscribers
  • Views 507 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CDCM6208 LVDS input termination

Marek Petrinec2
Prodigy 90 points
Other Parts Discussed in Thread: CDCM6208

Hello,

I would like to know if my circuit is right. Could someone from TI check it please? Also i would especcialy ask about PRI input LVDS buffer. Is it true LVDS input buffer? Cause iam using LVDS because of galvanic isolation and iam not sure if your device needs offset voltage or not. Driver of LVDS clock vill be FPGA Cyclone IV. Also i would like to ask about termination of secondary input where is used CRYSTEK oscilator. [04] - PLL.PDF

  • 0
    Prodigy 90 points
    could anybodey help me with termination of this ic? does this ic needs offset voltage for LVDS? also does it needs offset for hcmos? (secondary input with crystek osc) many thanks
  • 0 in reply to Marek Petrinec2
    TI__Mastermind 32575 points
    CDCM6208 inputs do not have internal DC biasing, so these DC offset needs to be applied externally on the CDCM6208-side of the AC coupling capacitors.

    For LVDS input on PRIREF, this can be done by providing a resistor biasing network to comply with the input common mode voltage spec (see datasheet).

    To meet the Vih/Vil specs for LVCMOS input on SECREF, you can use resistor biasing network after the AC coupling cap, or use DC-coupled interface between OSC output and SECREF_P input. In either DC or AC coupling cases, SECREF_N input should tied to GND via pulldown resistor.

    Alan