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LMK04826: output clock have jitter about every 1 to 5 second

user5305343
Prodigy 30 points
Part Number: LMK04826
Other Parts Discussed in Thread: AFE58JD28

Hi,

I'm using LMK04826 now and use it in 2 mode:

clock distribution mode, with 125MHz clock in Clkin1 pin, 41.667MHz clock out;

PLL2 only mode, with 100MHz clock in OSCin pin, 60MHz clock out;

The output clock in both modes have jitter in about every 1 to 5 second

How can I solve this problem?

Thanks a lot

  • 0
    TI__Guru** 110430 points

    Hi There,

    What is the output format? can you share the schematic?

  • 0 in reply to Noel Fung
    Prodigy 30 points

    Hi,

    The output format is LVDS.

    About the schematic, we just copy the AFE58JD28 LMK input part and remap the output part to connect more AFEs.

  • 0 in reply to user5305343
    TI__Guru** 110430 points

    Hi There,

    Your signal does not seem like a LVDS signal. Could you provide your schematic? You do not need to provide the complete schematic, I am only interested in the interconnection between LMK output and the receiver. 

    if you have the same periodic glitch even in distribution mode, I am sure that these glitches are coming from external force. For example, power supply.

  • 0 in reply to Noel Fung
    Prodigy 30 points

    Hi Noel,

    The signal is from the LVDS p/n-pin, I didn't detect the differential pair.

    I also tried to disconnect the capacitor between the LMK output and the receiver, then detect the LMK pin. It also has a similar jitter.

  • 0 in reply to user5305343
    TI__Guru** 110430 points

    Hi There,

    Try put the 100Ω resistor on the left hand side of the capacitor, this will ensure the LVDS driver has a current path between the output pins. 

    BTW, there are couple of issues with your schematic.

    You should not put a 50Ω shunt directly at the output of a CMOS XO (Y2), DC current flow could be very high. We suggest AC-couple the output to the 50Ω shunt.

    Is Y7 also a CMOS XO? If this is the case, you may need to reduce the voltage swing going to the OSCin* pin, the max. input swing is 2.4V.