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TPL5110: delaying the timed reset

Part Number: TPL5110

I see from the documentation that:  "An extended assertion of a logic HIGH at the DELAY/M_DRV pin will turn on the MOSFET for a time longer than the programmed time interval. DONE signals received while the DELAY/M_DRV is HIGH are ignored. If the DRV is already LOW (MOSFET ON) the manual power ON is ignored."

I am making remote blinds.  The microcontroller on the blinds needs to power up once per three seconds to look for a radio signal. If it is present, then it needs to drive a motor and take actions for 10 seconds.  Thus, I want the TPL5110 to power up the microcontroller once per three seconds, but if a signal is present then I cant have the microcontroller reset when the TPL5110 timer elapses in three seconds since the microcontroller needs to take actions for 10 seconds.   

Would the following work? I power the microcontroller off the DRV pin.  I set the resistance on the TPL DELAY pin for 3 seconds.  Every 3 seconds the TPL5110 turns the microcontroller on.  While the microcontroller is on, if it sees the radio signal, then it will use one of its GPIOs to bring the DELAY pin HIGH and keep it high until the microcontroller finishes its ten seconds of tasks.  Then the microcontroller changes that GPIO output to LOW (or changes it to a floating input) and uses another GPIO to bring the DONE pin HIGH to get the TPL5110 to cut power.  

  • Hi Jo,

    The scheme you outlined sounds like it would work. Your situation where it sees a radio signal would perform similarly to the red highlighted section of your related E2E.

    EDIT: actually, I believe I misunderstood the datasheet and the diagram... please see subsequent reply.

    Regards,

    Derek Payne

  • Jo,

    After reviewing the post, I believe I was mistaken: pulsing DELAY/M_DRV pin high while DRV is low will be ignored, and the timer will not be reset, so DRV would still be shut off after the 3s interval.

    As the linked E2E suggests, unless you know in advance that a cycle should remain active and have the ability to hold DELAY/M_DRV pin high through some other mechanism while DRV is high, the DELAY/M_DRV pulse is ignored.

    I believe you could accomplish the same thing by adding one resistor to the DRV/pass FET connection, and one NFET to the output. You would toggle the NFET gate high when a radio pulse is detected, and force override the DRV signal until complete. You would then disable the NFET and send the DONE signal. The resistor prevents the NFET from shorting out the DRV pin when it outputs high, but still allows DRV pin to control the state of the pass FET. Maybe this could also work with an open-drain output on a microcontroller and omitting the NFET, if the microcontroller output was exclusively open-drain and did not have any ESD structure pulling up to VCC. But for a conventional microcontroller push-pull output stage the NFET is required.

    Regards,

    Derek Payne

  • Are you saying the connection would be   DRV--->resistor------>NFET------>load   ?

  • Jo,

    Does this diagram clarify the connection I am suggesting? 10kΩ is selected as an arbitrary large value.

    Regards,

    Derek Payne